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blog: home logic: flesh out the writing around this buffered inverter chain

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colin 2022-07-13 14:48:16 -07:00
parent 0aa261ba07
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43
content/blog/DRAFT-2022-05-26-home-built-computation/index.md
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@ -289,10 +289,10 @@ each of these two outlined "inverters" carries only one bit, with the rest of th
you might think that when we cascade these devices, we could remove the input buffer of the second
device because it's already guarded by the output buffer of the first device.
unfortunately, that's not the case: i showed that buffer cores are needed when we discharge the inverter,
but after we discharge it we need to charge it _back_ to logic '1', and this requires an additional buffer.
but after we discharge it we need to charge it _back_ to logic '1', and that requires an additional buffer.
but this does present a problem: each stage of this chain performs 4 inversions -- so it's no longer
an inverter chain, but rather a shift register. we can solve this by inverting the wiring on 3 of these
but this does present a problem: each stage of this chain performs 4 inversions -- so externally it no longer
behaves as an inverter, but just a shift register. we can solve this by inverting the wiring on 3 of these
cores, and leaving just one inverting core:
<!-- there are other ways, too. we can have a 3-clock device if we switch to
@ -304,8 +304,8 @@ differential signals: +Vdd for logic '1' and -Vdd for logic '0'. but this requir
notice the wire sections which were previously blue but now red:
any pulses they carry are sent "into" the core (into the page)
instead of "out of" the core as before. hence, pulses on the red wires
have a tendency to write logic '1' to the core they feed into,
whereas the blue wires write logic '0' instead.
have a tendency to write logic '1' (CW) to the core they feed into,
whereas the blue wires write logic '0' (CCW) instead.
as data arrives into this device, it's immediately inverted, and will later be propagated downstream.
if we're deliberate with our control signals, we can cascade these inverter devices without issue.
@ -313,30 +313,33 @@ here's what that looks like over time:
![](staged-inverter-chain-clock0.svg)
TODO: rework this paragraph below to explain things left-to-right.
just prior to this moment, the last core of each buffer was holding S̄1 and S̄0, respectively.
now we're clearing those cores and dumping those values onto the output wires.
S̄1 now shows up at the input to the second device. that input, having an inverted winding,
forces its core into 1 - S̄1, or simply, S1.
the first device is fed new data at this moment, inverting and storing that signal as well.
TODO: CTL0 and CTL3 has wrong transition: should just copy the cycle4 diagram and change the numbers
TODO: the CTL0/CTL3 0->1 transitions are wrong.
S2 arrives as input to the first device, which can receive data because CTL0 is at 0V
(or even just left floating). this write polarizes the core away from logic '1', hence the core
is driven toward the inverse of S2, i.e. S̄2.
simultaneously, the fourth core was previously storing S̄1. it's actively driven back to 0,
dumping S̄1 onto its output. the second device behaves identically to the first, inverting
its S̄1 input back to S1 and simultaneously outputing S0.
over the next three CTL transitions, data is moved internally through the device.
these CTL transitions cause current to flow in the device's input/output loops,
but by watching the interface between these devices we can see that this only happens
when the adjacent device isn't open to writes (that's the point of our buffers).
![](staged-inverter-chain-clock1.svg)
![](staged-inverter-chain-clock2.svg)
you can see above that there's current in _every_ loop during this transition.
it's the single 0 -> 0 core at the end of each device here which prevents
the state from one device cross its way into the other device at this moment.
![](staged-inverter-chain-clock3.svg)
![](staged-inverter-chain-clock4.svg)
in effect, this is a chain of _two_ inverters,
where each inverter has four clock cycles of latency.
if we were to add an additional input winding to the first core in a group,
then that group would now serve as a NOR gate.
that last CTL transition is just a repeat of the first image.
if we were to add an additional input winding (blue wire) to the first core in a device,
then that device would now serve as a NOR gate.
so we've got a framework for cascading, synchronous logic: use this four-core device
as our primitive logic gate and arrange it into whatever circuit we want.
the control signals are nastier than with CMOS, but the concept's there.

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