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app: stacked_cores: prototype a 3-core/1-cycle inverter (51-xx) 

we vary the conductivities, as with 50-xx. the hope is that with a
multi-core approach like this we might get >> 1.0x amplification in the
unloaded setup, which we can place into a loaded circuit and deal with
the ~70% loading penalty.
This commit is contained in:
colin 2022-10-27 18:31:39 -07:00
parent 9c17d3b45d
commit 12f286c3c7
3 changed files with 106 additions and 4 deletions
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7
crates/applications/stacked_cores/scripts/plot_inverters.py
View File

@ -192,8 +192,9 @@ _48xx_study = from_params(
_49xx_study = from_params(
[
# slope ranges are measured from x=0 to x=0.2
# TODO
# y(0)=0.90, y(1)=0.99, slope0>0.28
SimParams50(5e2, 4e4, 4000, 200, 5, 1, 400, "2e10"),
# y(0)=0.79, y(1)=0.98, slope0=0.36 to 0.27
SimParams50(5e3, 4e4, 4000, 200, 5, 1, 400, "2e10"),
# y(0)=0.65, y(1)=0.95, slope0=0.44 to 0.31
SimParams50(5e3, 4e4, 4000, 200, 5, 1, 400, "1e10"),
@ -230,6 +231,10 @@ _49xx_study = from_params(
# SimParams50(1e4, 2e4, 2000, 100, 5, 1, 400, "2e10"),
# y(0)=0.30, y(1)=0.40, slope0>0.09
# SimParams50(2e4, 2e4, 2000, 100, 5, 1, 400, "1e10"),
SimParams51(1e3, 2e4, 2000, 100, 5, 1, 400, "2e10"),
SimParams51(2e3, 2e4, 2000, 100, 5, 1, 400, "2e10"),
SimParams51(5e3, 2e4, 2000, 100, 5, 1, 400, _3e10),
]
)

29
crates/applications/stacked_cores/scripts/stacked_cores_40xx_db.py
View File

@ -235,6 +235,23 @@ class SimParams50(SimParamsV3):
def t_mid(self) -> float:
return 4e-12 * self.clock_length_ps
class SimParams51(SimParamsV3):
@property
def run(self) -> str:
return "51"
@property
def is_inverter(self) -> bool:
return True
@property
def t_last(self) -> float:
return 2e-12 * self.clock_length_ps
@property
def t_init(self) -> float:
return 1e-12 * self.clock_length_ps
sims = [
# params, human friendly db name, normalization
(SimParams40(6, 1, 400, "5e10"), "fwd_40_6_3_1_5e10", 17000),
@ -442,6 +459,10 @@ sims = [
(SimParams50(5e2, 4e4, 4000, 200, 5, 1, 400, "2e10"), None, 20000),
(SimParams50(5e3, 4e4, 4000, 200, 5, 1, 400, "1e10"), None, 20000),
(SimParams50(5e3, 4e4, 4000, 200, 5, 1, 400, "2e10"), None, 20000),
(SimParams51(1e3, 2e4, 2000, 100, 5, 1, 400, "2e10"), None, 20000),
(SimParams51(2e3, 2e4, 2000, 100, 5, 1, 400, "2e10"), None, 20000),
(SimParams51(5e3, 2e4, 2000, 100, 5, 1, 400, _3e10), None, 20000),
]
measurements = { real.machine_name: [human, norm, None, None] for (real, human, norm) in sims }
@ -5136,4 +5157,12 @@ Piecewise(
)
""")
set_meas("51-0.0004rad-1000ctl_cond-20000coupling_cond-2000ps-100ps-5ctl-5coupling-3_1_winding-2e10-drive", """
Piecewise(
[
[ 16910, -16375 ], # 1.000
]
)
""")
if __name__ == '__main__': main()

74
crates/applications/stacked_cores/src/main.rs
View File

@ -1190,7 +1190,7 @@ fn drive_map_3stack_multi_clock_buffer(amp0: f32) -> [[ClockState; 3]; 5] {
}
#[allow(unused)]
fn drive_map_3stack_multi_clock_buffer_quick_one_cycle(amp0: f32, amp1: f32) -> [[ClockState; 3]; 5] {
fn drive_map_3stack_multi_clock_buffer_quick_one_cycle(amp0: f32) -> [[ClockState; 3]; 2] {
use ClockState as C;
// amplitudes are inverted from what you would expect.
// hold(-1) puts the core into a positive M
@ -5439,7 +5439,7 @@ fn main() {
}
}
}
if true {
if false {
for init_set in [
&[
// targeted
@ -5492,7 +5492,7 @@ fn main() {
][..],
] {
for (ctl_cond, coupling_cond, clock_duration, clock_decay, coupling_loops, s0_loops, s_major, cur_flt) in [
// prototypes
// y(0)=0.65, y(1)=0.95, slope0=0.44 to 0.31
(5e3, 4e4, ps(4000), ps(200), 5, 1, um(400), 1e10),
// worth pursuing in more detail:
@ -5557,6 +5557,74 @@ fn main() {
}
}
}
if true {
for init_set in [
&[
// targeted
][..],
&[
// establish the domain/range
1.00,
-1.00,
][..],
&[
0.00,
][..],
&[
-0.20,
-0.10,
0.10,
-0.05,
][..],
&[
0.05,
-0.15,
-0.25,
-0.35,
0.20,
-0.30,
][..],
] {
for (ctl_cond, coupling_cond, clock_duration, clock_decay, coupling_loops, s0_loops, s_major, cur_flt) in [
// from 50-xx
(1e3, 2e4, ps(2000), ps(100), 5, 1, um(400), 2e10),
(2e3, 2e4, ps(2000), ps(100), 5, 1, um(400), 2e10),
(5e3, 2e4, ps(2000), ps(100), 5, 1, um(400), 3e10),
// (2e3, 2e4, ps(2000), ps(100), 5, 1, um(400), 1e10),
] {
for &init_flt in init_set {
// coupling loops (M0 -> M1) + (M1 -> M2) + control slots
let slots_per_asym = 2*s0_loops;
let net_slots = 2*slots_per_asym + 1;
let mut params = params_v2
.with_clock_phase_duration(clock_duration)
.with_clock_decay(clock_decay)
.with_ctl_conductivity(ctl_cond)
.with_coupling_conductivity(coupling_cond)
.with_s_major(s_major)
.with_coupling_loops(coupling_loops)
.with_input_magnitude(cur_flt)
// control loops
.with_coupling(0, 0, 0, net_slots, CouplingMethod::Control)
.with_coupling(1, 1, 0, net_slots, CouplingMethod::Control)
.with_coupling(2, 2, 0, net_slots, CouplingMethod::Control)
;
params = couple_asymmetric_buffer(&params, 0 /* sender core */, s0_loops, 1 /* slot offset */, net_slots);
params = couple_asymmetric_buffer(&params, 1 /* sender core */, s0_loops, 1 + slots_per_asym /* slot offset */, net_slots);
let name = asymmetric_inverter_name_v3(
&params, "51", coupling_loops /* ctl loops */, coupling_loops, 2*s0_loops + 1, init_flt
);
run_sim(
&name,
drive_map_3stack_multi_clock_buffer_quick_one_cycle(init_flt),
params,
);
}
}
}
}
}