port: legacy sim accessors test to spirv

This commit is contained in:
2022-08-14 19:16:09 -07:00
parent f61c0aeb00
commit 19893157fa
2 changed files with 15 additions and 0 deletions

View File

@@ -1154,6 +1154,7 @@ mod test {
(energy_0, energy_1)
}
// PORT-STATUS: done
#[test]
fn accessors() {
let mut state = SimState::<R64, Static<R64>>::new(Index((15, 17, 19).into()), 1e-6);

View File

@@ -616,6 +616,20 @@ mod test {
use super::backend_agnostic::*;
use super::*;
#[test]
fn accessors() {
let size = Index::new(15, 17, 19);
let mut state = SpirvSim::<R32, FullyGenericMaterial<R32>, $backend>::new(size, 1e-6);
assert_eq!(state.width(), 15);
assert_eq!(state.height(), 17);
assert_eq!(state.depth(), 19);
assert_eq!(state.time(), 0.0);
// feat_size / C * courant: 1e-6 / 3e8 * 0.577
assert_eq!(state.timestep(), 0.0000000000000019246651);
state.step();
assert_eq!(state.time(), state.timestep());
}
#[test]
fn test_smoke_small() {
do_smoke_small::<$backend>();