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app: multi_core_inverter: fix up the drive sequence

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see the code comment for explanation.
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colin
2022-08-10 01:43:36 -07:00
parent 3998d72d02
commit 46a53a4dde
1 changed files with 20 additions and 13 deletions
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33
crates/applications/multi_core_inverter/src/main.rs
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@@ -140,25 +140,32 @@ fn main() {
driver.add_measurement(meas::CurrentLoop::new("sense3", sense3.clone()));
//////// create the stimuli
// CTL{n} effectively leads CTL{n-1}
// or: at time t, CTL{n} is at cycle[t+n]
// where cycle[t] is defined by CTL[0](t):
// 0, +Vdd, +Vdd, +Vdd
// TODO: this is wrong (as is the diagram in the blog)! CTL0, being an inverter,
// needs -Vdd to recharge to +polarization
let cycles = 4;
let duration = Seconds(clock_phase_duration * (cycles + 2) as f32);
// each row N denotes the drive currents at clock cycle N.
// each col M denotes the drive current at core M.
// this drive map is taken from the blog article as of 2022-08-09; it has noted errors
// let drive_map = [
// [1, 0, 1, 1],
// [1, 1, 0, 1],
// [1, 1, 1, 0],
// [0, 1, 1, 1i32],
// ];
// proposed drive map: the location where a core is charged to 1 requires a negative current.
let drive_map = [
[1, 0, 1, 1],
[1, 1, 0, 1],
[1, 1, 1, 0],
[0, 1, 1, 1i32],
[ 1, 0, 1, -1],
[-1, 1, 0, 1],
[ 1, -1, 1, 0],
[ 0, 1, -1, 1i32],
];
let cycles = drive_map.len() as u32;
let duration = Seconds(clock_phase_duration * (cycles + 2) as f32);
for cycle in 0..cycles {
for core in 0..4 {
let dir = drive_map[cycle as usize][core as usize];
// current polarity of the drive wires is inverted in this model v.s. the blog article,
// so invert our currents in order to achieve the magnetic states of the article.
let dir = -drive_map[cycle as usize][core as usize];
if dir != 0 {
// micro opt/safety: don't place zero-magnitude stimuli
driver.add_stimulus(input(&ctl(core), cycle, dir));