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app: multi-core-inverter: fix non-terminating drive signal

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colin
2022-08-22 01:41:20 -07:00
parent 232e0fdafb
commit 8268215441
1 changed files with 8 additions and 2 deletions
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10
crates/applications/multi_core_inverter/src/main.rs
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@@ -148,14 +148,20 @@ impl Params {
// simple square wave:
let amp = ty.as_signed_f32() * self.input_magnitude;
let start = self.clock_phase_duration * cycle as f32;
Exp::new_at(amp.cast(), start.cast(), 100f32.cast() /* very long decay */)
Exp::new(100f32.cast() /* very long decay */)
.scaled(amp.cast())
.gated(R::zero(), self.clock_phase_duration.cast())
.shifted(start.cast())
}
fn control_signal_release(&self, cycle: u32, ty: DriveDirection) -> ClockSegment {
// decaying exponential wave:
let amp = ty.as_signed_f32() * self.input_magnitude;
let start = self.clock_phase_duration * cycle as f32;
Exp::new_at(amp.cast(), start.cast(), self.clock_decay.cast())
Exp::new(self.clock_decay.cast() /* half life */)
.scaled(amp.cast())
.gated(R::zero(), self.clock_phase_duration.cast())
.shifted(start.cast())
}
}