move util/
out of coremem
and into its only user: buffer_proto5
This commit is contained in:
1
Cargo.lock
generated
1
Cargo.lock
generated
@@ -160,6 +160,7 @@ dependencies = [
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name = "buffer_proto5"
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version = "0.1.0"
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dependencies = [
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"bincode",
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"coremem",
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"log",
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"serde",
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@@ -5,6 +5,7 @@ authors = ["Colin <colin@uninsane.org>"]
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edition = "2021"
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[dependencies]
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bincode = "1.3" # MIT
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coremem = { path = "../../coremem" }
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log = "0.4"
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serde = "1.0"
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@@ -9,6 +9,7 @@ pub struct DiskCache<K, V, S=NoSupplier> {
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}
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impl<K: DeserializeOwned, V: DeserializeOwned> DiskCache<K, V, NoSupplier> {
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#[allow(dead_code)]
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pub fn new(path: &str) -> Self {
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Self::new_with_supplier(path, NoSupplier)
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}
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@@ -48,6 +49,7 @@ impl<K: Serialize, V: Serialize, S> DiskCache<K, V, S> {
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}
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impl<K: PartialEq + Serialize, V: Serialize + Clone, S> DiskCache<K, V, S> {
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#[allow(dead_code)]
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pub fn get_or_insert_with<F: FnOnce() -> V>(&mut self, k: K, f: F) -> V {
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if let Some(v) = self.get(&k) {
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return v.clone();
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@@ -10,10 +10,13 @@ use coremem::render::CsvRenderer;
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use coremem::sim::spirv::{SpirvSim, WgpuBackend};
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use coremem::sim::units::{Seconds, Time as _};
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use coremem::stim::{CurlStimulus, Exp1, Gated, Sinusoid1, TimeVarying as _};
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use coremem::util::cache::DiskCache;
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use log::{error, info, warn};
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use serde::{Deserialize, Serialize};
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mod cache;
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use cache::DiskCache;
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type Mat = IsoConductorOr<f32, Ferroxcube3R1MH>;
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#[allow(unused)]
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@@ -13,7 +13,6 @@ pub mod meas;
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pub mod render;
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pub mod sim;
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pub mod stim;
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pub mod util;
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pub use driver::*;
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pub use sim::*;
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@@ -1 +0,0 @@
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pub mod cache;
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