app: multi_core_inverter: try a 5-stage inverter (each stage inverts)
we're diverging from the blog pretty far now. but it turns out that, because of the inversion in Maxwell's $\nabla x E = -dB/dT$ equation, the trivial wiring actually leads to natural inverters.
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@@ -94,23 +94,30 @@ fn main() {
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let input_magnitude = 1.0e9;
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let clock_phase_duration = ps(2000);
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// 's' = core (ferromagnetic part)
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let s_major = um(160);
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let s_minor = um(30);
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// 'io' = drive/control wire
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let io_major = um(80);
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let io_minor = um(30);
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let coupling_major = um(130);
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let coupling_minor = um(30);
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// coords for core 'n'
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let sx = |n| um((n+1) * 400);
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let sy = um(400);
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let sz = um(280);
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// x-coord for the loop coupling core 'n' to core 'n+1'
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let couplingx = |n| sx(n) + um(200);
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let sim_bounds = Meters::new(sx(4), sy * 2.0, sz * 2.0);
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let sim_bounds = |num_cores| Meters::new(sx(num_cores), sy * 2.0, sz * 2.0);
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let sim_padding = Meters::new(um(80), um(80), um(80));
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let drive0 = Torus::new_xz(Meters::new(sx(0) - s_major, sy, sz), io_major, io_minor);
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let sense3 = Torus::new_xz(Meters::new(sx(3) + s_major, sy, sz), io_major, io_minor);
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// core '0' gets an external input in place of its coupling loop
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let input0 = Torus::new_xz(Meters::new(sx(0) - s_major, sy, sz), io_major, io_minor);
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// the last core gets an external output in place of its coupling loop
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let sense = |n| Torus::new_xz(Meters::new(sx(n) + s_major, sy, sz), io_major, io_minor);
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// control loop for core n (alternately called "drive" loop)
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let ctl = |n| Torus::new_yz(Meters::new(sx(n), sy + s_major, sz), io_major, io_minor);
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let s = |n| Torus::new_xy(Meters::new(sx(n), sy, sz), s_major, s_minor);
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// coupling(n) is the wire which couples core n into core n+1
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@@ -118,8 +125,7 @@ fn main() {
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let control_signal = |driver: &mut Driver<Sim>, region: &Torus, cycle: u32, ty: DriveType| {
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let area = region.cross_section();
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// negation because blog confuses current directions.
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let amp = -ty.direction() as f32 * input_magnitude / area;
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let amp = ty.direction() as f32 * input_magnitude / area;
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let start = clock_phase_duration * cycle as f32;
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if ty.is_hold() {
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// simple square wave:
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@@ -144,114 +150,98 @@ fn main() {
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// .shifted(clock_phase_duration * cycle as f32);
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};
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//////// define the control signals/transitions
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// each row N denotes the drive currents at clock cycle N.
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// each col M denotes the drive current at core M.
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use DriveType::*;
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let drive_map = [
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// charge each device to '1'
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[HoldHigh, HoldHigh, HoldHigh, HoldHigh, HoldHigh],
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// open S1 for write
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[HoldHigh, ReleaseHigh, HoldHigh, HoldHigh, HoldHigh],
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// write S0' => S1
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[HoldLow, Float, HoldHigh, HoldHigh, HoldHigh],
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// open S2 for write
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[HoldLow, Float, ReleaseHigh, HoldHigh, HoldHigh],
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// write S1' => S2
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[HoldLow, HoldLow, Float, HoldHigh, HoldLow],
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// open S3 for write
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[HoldLow, HoldLow, Float, ReleaseHigh, HoldLow],
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// write S2' => S3; RESET S0
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[HoldHigh, HoldLow, HoldLow, Float, HoldLow],
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// open S4 for write
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[HoldHigh, HoldLow, HoldLow, Float, ReleaseLow],
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// write S3' => S4; RESET S1
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[HoldHigh, HoldHigh, HoldLow, HoldLow, Float],
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// open S0 for write
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[ReleaseHigh, HoldHigh, HoldLow, HoldLow, Float],
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// write S4' => output; RESET S2
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[Float, HoldHigh, HoldHigh, HoldLow, HoldLow],
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// open S1 for write
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[Float, ReleaseHigh, HoldHigh, HoldLow, HoldLow],
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];
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let wire_mat = IsomorphicConductor::new(1e6f32.cast::<R>());
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// let ferro_mat = wire_mat;
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let ferro_mat = Ferroxcube3R1MH::new();
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let num_cores = drive_map[0].len();
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let last_core = num_cores - 1;
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let mut driver = Driver::new(Sim::new(
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sim_bounds.to_index(feat_size), feat_size,
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sim_bounds(num_cores).to_index(feat_size), feat_size,
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));
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driver.add_classical_boundary_explicit::<R, _>(sim_padding);
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//////// create the wires and toroids
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driver.fill_region(&drive0, wire_mat);
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driver.fill_region(&sense3, wire_mat);
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for core in 0..4 {
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driver.fill_region(&input0, wire_mat);
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driver.fill_region(&sense(last_core), wire_mat);
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for core in 0..num_cores {
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driver.fill_region(&s(core), ferro_mat);
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driver.fill_region(&ctl(core), wire_mat);
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if core != 3 {
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if core != last_core {
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driver.fill_region(&coupling(core), wire_mat);
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}
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}
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//////// monitor some measurements
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// driver.add_measurement(meas::CurrentLoop::new("drv0", drive0.clone()));
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for core in 0..4 {
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// driver.add_measurement(meas::CurrentLoop::new("input0", input0.clone()));
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for core in 0..num_cores {
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driver.add_measurement(meas::CurrentLoop::new(
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&format!("drive{}", core),
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ctl(core),
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));
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}
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for core in 0..3 {
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driver.add_measurement(meas::CurrentLoop::new(
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&format!("sense{}", core),
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coupling(core),
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));
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for core in 0..num_cores {
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let name = format!("sense{}", core);
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if core != last_core {
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driver.add_measurement(meas::CurrentLoop::new(
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&name, coupling(core),
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));
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} else {
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driver.add_measurement(meas::CurrentLoop::new(
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&name, sense(core),
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));
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}
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}
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for core in 0..4 {
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for core in 0..num_cores {
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driver.add_measurement(meas::MagneticLoop::new(
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&format!("state{}", core),
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s(core),
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));
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}
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driver.add_measurement(meas::CurrentLoop::new("sense3", sense3.clone()));
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//////// create the stimuli
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// each row N denotes the drive currents at clock cycle N.
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// each col M denotes the drive current at core M.
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// this drive map is taken from the blog article as of 2022-08-09; it has noted errors
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// let drive_map = [
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// [1, 0, 1, 1],
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// [1, 1, 0, 1],
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// [1, 1, 1, 0],
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// [0, 1, 1, 1i32],
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// ];
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// proposed drive map: the location where a core is charged to 1 requires a negative current.
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// let drive_map = [
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// [ 1, 0, 1, 1], // clear S0 -> S1; hold S2, S3
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// [-1, 1, 0, 1], // clear S1 -> S2; hold S3; reset S0
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// [-1, 1, 1, 0], // clear S2 -> S3; hold S0 (high), S1
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// [ 0, 1, -1, 1i32], // clear S3 -> Sn; hold S1, S2 (S0 gets new input
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// ];
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// the above drive map has some implicit requirement of clock lag. it won't work with perfectly
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// square clocks. here's a realizable drive map:
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// #[allow(non_snake_case)]
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// let F = 0; // indicates a gate which has been driven to a known value and is now floating
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// #[allow(non_snake_case)]
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// let D = 0; // indicates a gate which carries data.
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// let drive_map = [
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// [-1, 1, 1, 1], // initial state: S0=1, S1=S2=S3=0
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// [-1, F, 1, 1], // open S1 for write
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// [ 1, D, 1, 1], // clear S0 -> S1; hold S2, S3
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// [ 1, D, F, 1], // open S2 for write
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// [-1, 1, D, 1], // clear S1 -> S2; hold S3; reset S0
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// [-1, 1, D, F], // open S3 for write
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// [-1, 1, 1, D], // clear S2 -> S3; hold S0 (high), S1
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// [ F, 1, 1, D], // open S0 for write (not used in this demo)
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// [ D, 1, 1, 1i32], // clear S3 -> Sn; hold S1, S2 (S0 gets new input)
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// [ D, F, 1, 1i32], // open S1 for write (not used; for completeness)
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// ];
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use DriveType::*;
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let drive_map = [
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[HoldLow, HoldHigh, HoldHigh, HoldHigh], // initial state: S0=1, S1=S2=S3=0
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[HoldLow, ReleaseHigh, HoldHigh, HoldHigh], // open S1 for write
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[HoldHigh, Float, HoldHigh, HoldHigh], // clear S0 -> S1; hold S2, S3
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[HoldHigh, Float, ReleaseHigh, HoldHigh], // open S2 for write
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[HoldHigh, HoldHigh, Float, HoldHigh], // clear S1 -> S2; hold S0, S3
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// NB: bonus clock! we have to reset S0 before opening S3, else writeback from next stage
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[HoldLow, HoldHigh, Float, HoldHigh], // reset S0; hold S1, S3
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[HoldLow, HoldHigh, Float, ReleaseHigh], // open S3 for write
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[HoldLow, HoldHigh, HoldHigh, Float], // clear S2 -> S3; hold S0 (high), S1
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[ReleaseLow, HoldHigh, HoldHigh, Float], // open S0 for write (not used in this demo)
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[Float, HoldHigh, HoldHigh, HoldHigh], // clear S3 -> Sn; hold S1, S2 (S0 gets new input)
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[Float, ReleaseHigh, HoldHigh, HoldHigh], // open S1 for write (not used; for completeness)
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];
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let cycles = drive_map.len() as u32;
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let duration = Seconds(clock_phase_duration * (cycles + 3) as f32);
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for cycle in 0..cycles {
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for core in 0..4 {
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for core in 0..num_cores {
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// current polarity of the drive wires is inverted in this model v.s. the blog article,
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// so invert our currents in order to achieve the magnetic states of the article.
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let sig = drive_map[cycle as usize][core as usize];
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@@ -259,7 +249,7 @@ fn main() {
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}
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}
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let prefix = "out/applications/multi_core_inverter/8/";
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let prefix = "out/applications/multi_core_inverter/9/";
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let _ = std::fs::create_dir_all(&prefix);
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// driver.add_state_file(&*format!("{}state.bc", prefix), 9600);
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driver.add_serializer_renderer(&*format!("{}frame-", prefix), 400, None);
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