app: stacked_cores: add a 3rd core to the mix

crates/applications/stacked_cores/src/main.rs

@@ -118,17 +118,20 @@ impl Params {
     fn s(&self, n: u32) -> Torus {
         Torus::new_xy(Meters::new(self.sx(), self.sy(), self.sz(n)), self.s_major, self.s_minor)
     }
-    fn coupling_angle(&self, loop_: u32) -> f32 {
-        let loop_ = match self.coupling_loops % 2 {
-            // we want to keep the left edge open, which means sometimes offsetting.
-            0 => loop_ as f32 + 0.5,
-            _not_zero => loop_ as f32,
-        };
-        loop_ / self.coupling_loops as f32 * f32::two_pi()
+    fn coupling_angle(&self, set_id: u32, loop_: u32) -> f32 {
+        // coupling onto 2 cores, plus 1 control and an optional sense.
+        let total_loops = self.coupling_loops * 2 + 2;
+        // + 1 because we reserve loop 0 for control.
+        let mut idx = loop_ * 2 + 1 + set_id;
+        // reserve idx = 50% for sense wire.
+        if idx >= total_loops / 2 {
+            idx += 1;
+        }
+        idx as f32 / total_loops as f32 * f32::two_pi()
     }
     /// coupling(n) is the wire which couples core n into core n+1
     fn coupling(&self, n: u32, loop_: u32) -> Translate<Rotate<ElongatedTorus>> {
-        let angle = self.coupling_angle(loop_);
+        let angle = self.coupling_angle(n, loop_);
         Translate::new(
             Rotate::about_z(
                 angle,
@@ -200,22 +203,42 @@ impl Params {
 fn drive_map_isolated_inv() -> [[ClockState; 2]; 6] {
     use ClockState::*;
     [
-        // charge each device to '1'
+        // charge S0 to '1', S1 to '0'
         [HoldHigh,   HoldLow   ],
         // let the cores settle
         [ReleaseHigh,ReleaseLow],
-        // write S0 -> S1. S1 should be *cleared* to 0.
+        // write S0 -> S1. S1 should be copied to 1
         [HoldLow,    Float      ],
 
         // charge S0=0, reset S1 for next write
         [HoldLow,    HoldLow   ],
         // let the cores settle
         [ReleaseLow, ReleaseLow],
-        // write S0 -> S1. S1 should *keep its state* of 1.
+        // write S0 -> S1. S1 should *keep its state* of 0
         [HoldLow,    Float      ],
     ]
 }
 
+#[allow(unused)]
+fn drive_map_3stack() -> [[ClockState; 3]; 6] {
+    use ClockState::*;
+    [
+        // charge S1 to '1', S0/S2 to '0'
+        [HoldLow,    HoldHigh,   HoldLow   ],
+        // let the cores settle
+        [ReleaseLow, ReleaseHigh,ReleaseLow],
+        // write S1 -> S0/S2. S0/S2 should be copied to 1
+        [Float,      HoldLow,    Float      ],
+
+        // charge S1=0, reset S0/S2 for next write
+        [HoldLow,    HoldLow,    HoldLow   ],
+        // let the cores settle
+        [ReleaseLow, ReleaseLow, ReleaseLow],
+        // write S1 -> S0/S2. S0/S2 should *keep its state* of 0
+        [Float,      HoldLow,    Float      ],
+    ]
+}
+
 fn main() {
     coremem::init_logging();
     // coremem::init_debug();
@@ -272,7 +295,7 @@ fn main() {
             p17x.with_coupling_loops(6),
         );
     }
-    if true {
+    if false {
         let p3xx = params
             .with_clock_phase_duration(ps(2000))
             .with_clock_decay(ps(100))
@@ -332,6 +355,61 @@ fn main() {
             p3xx.with_coupling_loops(32),
         );
     }
+    if true {
+        let p4xx = params
+            .with_clock_phase_duration(ps(1000))
+            .with_clock_decay(ps(50))
+            .with_input_magnitude(8e10)
+            .with_ctl_conductivity(5e2)
+            .with_coupling_conductivity(5e3)
+            .with_s_major(um(400))
+        ;
+        run_sim(
+            "401-1loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(1),
+        );
+        run_sim(
+            "402-2loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(2),
+        );
+        run_sim(
+            "404-4loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(4),
+        );
+        run_sim(
+            "406-6loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(6),
+        );
+        run_sim(
+            "408-8loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(8),
+        );
+        run_sim(
+            "410-10loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(10),
+        );
+        run_sim(
+            "412-12loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(12),
+        );
+        run_sim(
+            "416-16loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(16),
+        );
+        run_sim(
+            "420-20loops",
+            drive_map_3stack(),
+            p4xx.with_coupling_loops(20),
+        );
+    }
     // run_sim(
     //     "76-2ns-100ps-1e10A-1e3pctl-1e4pcpl-4loops",
     //     drive_map_isolated_inv(),