45d2de29c6
rename 'coremem_types' -> 'coremem_cross' to better reflect its purpose
2022-07-28 15:40:23 -07:00
07dfb9d852
spirv: add R32 support to the GPU code
2022-07-28 13:18:14 -07:00
568d61c598
spirv: remove the Optionality around entry points: compute them statically with traits
2022-07-27 12:32:43 -07:00
baaeeb9463
spirv_backend: no need to re-export glam
2022-07-27 12:13:01 -07:00
c85bee20f5
replace some assert's with debug_assert's; slightly more optimal Optional impls
2022-07-27 12:07:30 -07:00
f6a585852e
move the dimensioned operations out of the sim adapters and into step.rs
2022-07-26 18:43:41 -07:00
00dcfb170a
spirv_backend/support.rs: remove the re-export of DimensionedSlice
...
also add some docs
2022-07-26 18:08:03 -07:00
dbd666d272
move the dimensioned indexing out of spirv_backend and into coremem_types
...
this allows us to use it from the CPU implementation.
2022-07-26 18:03:21 -07:00
d93d14d260
spirv_backend: use RuntimeArray to remove all this UnsizedArray stuff
2022-07-26 15:58:23 -07:00
09f7c8acb9
spirv_backend: support: remove unused helpers
2022-07-26 13:36:42 -07:00
6e4133db4d
spirv backend: simplify the adapt.rs indexing by using the constructors previously created
2022-07-26 13:29:39 -07:00
8a16a5ce30
lift SimMeta from spirv_backend -> coremem_types
2022-07-25 00:52:11 -07:00
15aaa3e893
move spirv_backend/sim.rs -> coremem_types/step.rs
2022-07-25 00:40:27 -07:00
5490634fe7
move Optional out of spirv_backend and into coremem_types
2022-07-25 00:35:04 -07:00
9c7ef7ec88
spirv_backend: split the array operations out of sim.rs -> adapt.rs
2022-07-25 00:28:03 -07:00
8ab89640f2
spirv_backend: split out some of the spirv entry point adapters into adapt.rs
2022-07-25 00:21:20 -07:00
ebd2762d7a
spirv: sim: adjust so Step{E,H}Context does not use ArrayHandle
...
the specific way to accomplish this is touchy.
see <https://github.com/EmbarkStudios/rust-gpu/issues/312#issuecomment-738824131 >:
> So I'd say placing any of the spirv_std::storage_class types into an aggregate (including capturing it in a closure) is unsupported for now
in our specific case, we can't return a tuple where one element is a `&`
to a spirv Input, and another element is a `&mut` to a spirv Output.
when we have a struct, it can enclose either ONLY inputs,
or ONLY outputs -- not a mix.
i'm not 100% on how the Serialized stuff works, since it appears to
violate that. i guess that's exactly what this ArrayHandle stuff
achieves though.
2022-07-24 22:57:41 -07:00
05f5f75dd3
spirv: remove the ArrayHandleMut artifacts in Step{H,E}Context
...
this will make it easier to reuse these blocks on the CPU side.
2022-07-24 22:17:44 -07:00
b70cafa205
spirv support: fix an overly-constrained lifetime parameter in the array index fn
2022-07-24 21:51:20 -07:00
4a6a43fb31
plumb the R type parameter through spirv code
2022-07-22 16:21:03 -07:00
66ccbd1ada
spirv: remove mat.rs and reuse coremem_types::mat everywhere
2022-07-22 15:22:09 -07:00
847b95f036
replace the FullyGenericMaterial in spirv with an analog type from coremem_types
...
this represents the last spirv-specific material.
next steps are to start removing the materials from `coremem` itself
(i.e. re-exporting more from `coremem_types::mat`).
2022-07-22 02:56:00 -07:00
f8fccd957a
coremem_types: IsomorphicConductor, AnisomorphicConductor are now used by both spirv and cpu impls
2022-07-19 02:08:22 -07:00
716e0e12b4
move Ferroxcube3R1MH from spirv_bindings to coremem_types::mat
2022-07-18 15:33:47 -07:00
d005256459
move MBPgram, MHPgram out of spirv_backend into coremem_types::mat
...
later this can be shared with CPU backend.
2022-07-18 15:27:31 -07:00
b8bcd68b98
spirv_backend: use Real:: constants instead of inlined ones
2022-07-18 15:10:57 -07:00
57338bcb4a
migrate Conductor material from spirv_backend to coremem_types
2022-07-18 14:41:27 -07:00
7d2a3baadc
spirv: migrate Material trait to types, and parameterize by R
2022-07-18 14:33:09 -07:00
35251f5a7f
coremem_types: move Vec3u under the vec:: namespace
...
it's conceivable that Vec3u could be merged with Vec3 someday.
best to keep them in the same namespace, to make any such effort easier.
2022-07-18 14:23:35 -07:00
19f00c9076
spirv_backend: remove Vec3Std and use coremem_types::Vec3 everywhere
2022-07-18 13:51:11 -07:00
d7d8be62d1
spirv_backend: remove UVec3Std in favor of Vec3u
2022-07-18 13:39:15 -07:00
b4783df134
spirv_backend: remove dead-code
2022-07-18 13:34:10 -07:00
4378f33eb9
spirv_backend: strip out the glam stuff, except for the lib.rs interface
2022-07-18 01:48:19 -07:00
97c2813c9d
coremem_types: hide Serialize/Deserialize behind a serde feature flag
...
- this flag is disabled in spirv_backend.
- spirv_backend currently errors in core::fmt stuff. may try hiding fmt
behind a feature_flag.
2022-07-17 23:44:14 -07:00
5f03cfbec0
remove unused spirv_backend/src/main.rs file
2022-07-06 00:29:05 -07:00
5b99d30cda
restructure this multi-crate project to use Cargo's "workspace" feature
...
this solves an issue in the Nix build, where managing multiple
Cargo.lock files is otherwise tricky. it causes (or fails to fix?) an adjacent issue where
the spirv builder doesn't seem to have everything it needs vendored.
2022-07-05 17:34:21 -07:00
