6d73150fb6README: fix up stale paths, material referencescolin2022-12-07 09:41:38 +00:00
ed55cdfe10app: stacked_cores: 61-xx: complete more experiments; start ones with only symmetric couplingcolin2022-11-26 03:42:10 +00:00
1c9527bb63app: stacked cores: 61-xx: complete more runscolin2022-11-24 11:13:53 +00:00
06aaf55e30app: stacked_cores: 61-xx: more experimentscolin2022-11-22 12:56:01 +00:00
0d62b60423app: stacked_cores: 61-xx: complete more runscolin2022-11-22 00:25:52 +00:00
7bb8199b02app: stacked_cores: 61-xx: complete more runscolin2022-11-19 11:18:24 +00:00
cca6a7c8cdapp: stacked_cores: complete more 61-xx runscolin2022-11-18 23:54:34 +00:00
9cb9c4dd66app: stacked_cores: 61-xx: complete a few first-pass runs over an alternatively-parameterized complementary buffercolin2022-11-18 10:20:49 +00:00
da199568ffapp: stacked_cores: 53-xx: do another run with greater asymmetrycolin2022-11-18 02:47:09 +00:00
eccd865cf7app: stacked_cores: 60-xx: new experiment that tries moving a value along a 4-core loopcolin2022-11-17 23:28:49 +00:00
e13ddbdc1fapp: stacked_cores: complete more 59-xx runscolin2022-11-17 09:45:19 +00:00
38aa677aadapp: stacked_cores: complete some 59-xx runscolin2022-11-17 01:17:42 +00:00
a2a851b26fapp: stacked_cores: 58-xx: try merging cores via a complementary buffercolin2022-11-16 12:29:27 +00:00
9d4e245388app: stacked_cores: new 58-xx sim which tries a complementary buffer into a pre-charged outputcolin2022-11-11 22:59:57 +00:00
6e198caaa3fix "reset" -> "set" typo in SR latch examplecolin2022-11-11 05:28:54 +00:00
b7112fab86app: stacked_cores: 57xx: do some runs where only one pos core is wired into the outputcolin2022-11-11 03:35:24 +00:00
ea6799b764app: stacked_cores: new 57-xx experiment: complementary buffer with doubled inputscolin2022-11-10 01:23:02 +00:00
4539cb18feapp: stacked_cores: 56-xx: complete a few more runscolin2022-11-09 03:36:04 +00:00
7443599054app: stacked_cores: new 56-xx sim for complementary logic using multiple input corescolin2022-11-09 01:20:15 +00:00
df68100f82app: stacked_cores: define a fork -> join simcolin2022-11-08 09:23:28 +00:00
be172d4371remove the 'license' sectioncolin2022-11-07 03:19:53 -08:00
4407a8d3f7app: stacked_cores: 53-xx: complete some more runs, including one where inputs are uncoupledcolin2022-11-07 02:12:49 -08:00
16525127a1app: stacked_cores: 53-xx: complete a run which uses pos-windings != neg-windingscolin2022-11-05 18:54:10 -07:00
af4b5ffa32app: stacked_cores: 53-xx: complete a 1:1 coupled buffercolin2022-11-05 02:59:10 -07:00
1742172e6capp: stacked_cores: 53-xx: add a 5:1 buffercolin2022-11-04 06:11:08 -07:00
3ebcc550a0app: stacked_cores: 53-xx: better constrain the interpolation, and plot slopecolin2022-11-04 06:10:04 -07:00
373c80793fapp: stacked_cores: improve the 52-xx plotting/interpolationcolin2022-11-04 03:22:42 -07:00
df828b6299app: stacked_cores: create a plot_53xx and refactor the surroundingscolin2022-11-03 21:21:07 -07:00
8a8823ffd8app: stacked_cores: more 48-xx runs where we vary the coupling conductivity separate from the control conductivitycolin2022-10-21 19:19:55 -07:00
75a88887f0app: stacked_cores: 48-xx: simulate a few more variantscolin2022-10-21 09:54:20 -07:00
3dbdead1cbapp: stacked_cores: 48-xx: complete a few more runscolin2022-10-21 05:13:28 -07:00
daf50324d7app: stacked_cores: complete more 48-xx runscolin2022-10-21 01:00:46 -07:00
6f57e17befapp: stacked_cores: 48-xx: add some runscolin2022-10-17 06:51:48 -07:00
7c0151220capp: stacked_cores: new 48-xx sim which varies conductivities on a 2-core buffercolin2022-10-17 04:28:13 -07:00
ee74163131app: stacked_cores: complete a few runs of 46-xx where the output is floatingcolin2022-10-17 03:40:03 -07:00
760dd0070fapp: stacked_cores: complete a few more 46-xx runscolin2022-10-16 23:18:33 -07:00
ff2c79162capp: stacked_cores: 47-xx: cascade two buffers and vary their parameterizationcolin2022-10-16 17:21:10 -07:00