Merge patch series "Add PCIe support for TI AM64 SoC"

Hrushikesh Salunke <h-salunke@ti.com> says:

TI's AM64 SoC has a single instance of Cadence PCIe Controller. This
series enables support for PCIe in AM64 SoC and to configure it in
Root-Complex mode of operation.

Link: https://lore.kernel.org/r/20250416120830.138965-1-h-salunke@ti.com

configs/am64x_evm_a53_defconfig

@@ -32,6 +32,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
+CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
@@ -68,6 +69,12 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y
 CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_UBI=y
@@ -130,6 +137,9 @@ CONFIG_PHY_TI_DP83869=y
 CONFIG_PHY_FIXED=y
 CONFIG_TI_AM65_CPSW_NUSS=y
 CONFIG_TI_ICSSG_PRUETH=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI_CONFIG_HOST_BRIDGE=y
+CONFIG_PCIE_CDNS_TI=y
 CONFIG_PHY=y
 CONFIG_SPL_PHY=y
 CONFIG_PHY_CADENCE_TORRENT=y

drivers/pci/pcie_cdns_ti.c

@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/log2.h>
+#include <linux/sizes.h>
 #include <power-domain.h>
 #include <regmap.h>
 #include <syscon.h>
@@ -834,11 +835,21 @@ static const struct pcie_cdns_ti_data j7200_pcie_rc_data = {
 	.max_lanes = 2,
 };
 
+static const struct pcie_cdns_ti_data am64_pcie_rc_data = {
+	.mode = PCIE_MODE_RC,
+	.quirk_detect_quiet_flag = true,
+	.max_lanes = 1,
+};
+
 static const struct udevice_id pcie_cdns_ti_ids[] = {
 	{
 		.compatible = "ti,j7200-pcie-host",
 		.data = (ulong)&j7200_pcie_rc_data,
 	},
+	{
+		.compatible = "ti,am64-pcie-host",
+		.data = (ulong)&am64_pcie_rc_data,
+	},
 	{},
 };