Merge patch series "Add PCIe support for TI AM64 SoC"
Hrushikesh Salunke <h-salunke@ti.com> says: TI's AM64 SoC has a single instance of Cadence PCIe Controller. This series enables support for PCIe in AM64 SoC and to configure it in Root-Complex mode of operation. Link: https://lore.kernel.org/r/20250416120830.138965-1-h-salunke@ti.com
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@@ -32,6 +32,7 @@ CONFIG_SPL_FS_FAT=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_SPL_SPI=y
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CONFIG_PCI=y
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
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@@ -68,6 +69,12 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y
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CONFIG_CMD_NVEDIT_EFI=y
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CONFIG_CMD_NVEDIT_EFI=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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CONFIG_CMD_EFIDEBUG=y
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CONFIG_CMD_EFIDEBUG=y
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CONFIG_CMD_UBI=y
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CONFIG_CMD_UBI=y
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@@ -130,6 +137,9 @@ CONFIG_PHY_TI_DP83869=y
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CONFIG_PHY_FIXED=y
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CONFIG_PHY_FIXED=y
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CONFIG_TI_AM65_CPSW_NUSS=y
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CONFIG_TI_AM65_CPSW_NUSS=y
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CONFIG_TI_ICSSG_PRUETH=y
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CONFIG_TI_ICSSG_PRUETH=y
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CONFIG_NVME_PCI=y
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CONFIG_PCI_CONFIG_HOST_BRIDGE=y
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CONFIG_PCIE_CDNS_TI=y
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CONFIG_PHY=y
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CONFIG_PHY=y
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CONFIG_SPL_PHY=y
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CONFIG_SPL_PHY=y
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CONFIG_PHY_CADENCE_TORRENT=y
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CONFIG_PHY_CADENCE_TORRENT=y
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@@ -19,6 +19,7 @@
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/ioport.h>
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#include <linux/log2.h>
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#include <linux/log2.h>
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#include <linux/sizes.h>
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#include <power-domain.h>
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#include <power-domain.h>
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#include <regmap.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <syscon.h>
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@@ -834,11 +835,21 @@ static const struct pcie_cdns_ti_data j7200_pcie_rc_data = {
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.max_lanes = 2,
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.max_lanes = 2,
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};
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};
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static const struct pcie_cdns_ti_data am64_pcie_rc_data = {
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.mode = PCIE_MODE_RC,
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.quirk_detect_quiet_flag = true,
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.max_lanes = 1,
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};
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static const struct udevice_id pcie_cdns_ti_ids[] = {
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static const struct udevice_id pcie_cdns_ti_ids[] = {
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{
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{
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.compatible = "ti,j7200-pcie-host",
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.compatible = "ti,j7200-pcie-host",
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.data = (ulong)&j7200_pcie_rc_data,
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.data = (ulong)&j7200_pcie_rc_data,
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},
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},
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{
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.compatible = "ti,am64-pcie-host",
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.data = (ulong)&am64_pcie_rc_data,
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},
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{},
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{},
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};
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};
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