Merge patch series "MIPS: Boston: Various enhancements"

Jiaxun Yang <jiaxun.yang@flygoat.com> says: This is a huge series which promoted MIPS/Boston target into a usable state, with fixes to drivers and general framework issues I found in this process. I also converted the target to OF_UPSTREAM. This target is covered by QEMU, to test on QEMU: ``` make boston64r6el_defconfig make qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic ``` Link: https://lore.kernel.org/r/20240517-boston-v3-0-1ea7d23f4a1d@flygoat.com
2025-04-22 15:13:21 -06:00
parent bf2db18116 baf4bdcded
commit 20fcb6305e
27 changed files with 231 additions and 309 deletions
--- a/.mailmap
+++ b/.mailmap
@@ -96,7 +96,8 @@ This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@
 Padmarao Begari <padmarao.begari@amd.com> <padmarao.begari@microchip.com>
 Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
 Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
-Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
+Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
+Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
 Philipp Tomsich <philipp.tomsich@vrull.eu> <philipp.tomsich@theobroma-systems.com>
 Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
 Prabhakar Kushwaha <prabhakar@freescale.com>
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -146,7 +146,35 @@ config TARGET_BOSTON
 	select SUPPORTS_CPU_MIPS64_R6
 	select SUPPORT_BIG_ENDIAN
 	select SUPPORT_LITTLE_ENDIAN
+	imply OF_UPSTREAM
+	imply BOOTSTD_FULL
+	imply CLK
+	imply CLK_BOSTON
 	imply CMD_DM
+	imply AHCI
+	imply AHCI_PCI
+	imply CFI_FLASH
+	imply MTD_NOR_FLASH
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply PCH_GBE
+	imply PCI
+	imply PCI_XILINX
+	imply PCI_INIT_R
+	imply SCSI
+	imply SCSI_AHCI
+	imply SYS_NS16550
+	imply SYSRESET
+	imply SYSRESET_CMD_POWEROFF
+	imply SYSRESET_SYSCON
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_EHCI_PCI
+	imply USB_XHCI_HCD
+	imply USB_XHCI_PCI
+	imply CMD_USB

 config TARGET_XILFPGA
 	bool "Support Imagination Xilfpga"
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -3,7 +3,6 @@
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
 dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
-dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
 dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
--- a/arch/mips/dts/boston-u-boot.dtsi
+++ b/arch/mips/dts/boston-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&plat_regs {
+	compatible = "img,boston-platform-regs", "syscon", "simple-mfd";
+	bootph-all;
+};
+
+&clk_boston {
+	bootph-all;
+};
--- a/arch/mips/dts/img,boston.dts
+++ b/arch/mips/dts/img,boston.dts
@@ -1,222 +0,0 @@
-/dts-v1/;
-
-#include <dt-bindings/clock/boston-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/mips-gic.h>
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	compatible = "img,boston";
-
-	chosen {
-		stdout-path = &uart0;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "img,mips";
-			reg = <0>;
-			clocks = <&clk_boston BOSTON_CLK_CPU>;
-		};
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x10000000>;
-	};
-
-	gic: interrupt-controller {
-		compatible = "mti,gic";
-
-		interrupt-controller;
-		#interrupt-cells = <3>;
-
-		timer {
-			compatible = "mti,gic-timer";
-			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-			clocks = <&clk_boston BOSTON_CLK_CPU>;
-		};
-	};
-
-	pci0: pci@10000000 {
-		status = "disabled";
-		compatible = "xlnx,axi-pcie-host-1.00.a";
-		device_type = "pci";
-		reg = <0x10000000 0x2000000>;
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-		#interrupt-cells = <1>;
-
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
-
-		ranges = <0x02000000 0 0x40000000
-			  0x40000000 0 0x40000000>;
-
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pci0_intc 0>,
-				<0 0 0 2 &pci0_intc 1>,
-				<0 0 0 3 &pci0_intc 2>,
-				<0 0 0 4 &pci0_intc 3>;
-
-		pci0_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-		};
-	};
-
-	pci1: pci@12000000 {
-		status = "disabled";
-		compatible = "xlnx,axi-pcie-host-1.00.a";
-		device_type = "pci";
-		reg = <0x12000000 0x2000000>;
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-		#interrupt-cells = <1>;
-
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
-
-		ranges = <0x02000000 0 0x20000000
-			  0x20000000 0 0x20000000>;
-
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pci1_intc 0>,
-				<0 0 0 2 &pci1_intc 1>,
-				<0 0 0 3 &pci1_intc 2>,
-				<0 0 0 4 &pci1_intc 3>;
-
-		pci1_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-		};
-	};
-
-	pci2: pci@14000000 {
-		compatible = "xlnx,axi-pcie-host-1.00.a";
-		device_type = "pci";
-		reg = <0x14000000 0x2000000>;
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-		#interrupt-cells = <1>;
-
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
-
-		ranges = <0x02000000 0 0x16000000
-			  0x16000000 0 0x100000>;
-
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pci2_intc 0>,
-				<0 0 0 2 &pci2_intc 1>,
-				<0 0 0 3 &pci2_intc 2>,
-				<0 0 0 4 &pci2_intc 3>;
-
-		pci2_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-		};
-
-		pci2_root@0,0,0 {
-			compatible = "pci10ee,7021";
-			reg = <0x00000000 0 0 0 0>;
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			#interrupt-cells = <1>;
-
-			eg20t_bridge@1,0,0 {
-				compatible = "pci8086,8800";
-				reg = <0x00010000 0 0 0 0>;
-
-				#address-cells = <3>;
-				#size-cells = <2>;
-				#interrupt-cells = <1>;
-
-				eg20t_mac@2,0,1 {
-					compatible = "pci8086,8802";
-					reg = <0x00020100 0 0 0 0>;
-					phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>;
-				};
-
-				eg20t_gpio: eg20t_gpio@2,0,2 {
-					compatible = "pci8086,8803";
-					reg = <0x00020200 0 0 0 0>;
-
-					gpio-controller;
-					#gpio-cells = <2>;
-				};
-
-				eg20t_i2c@2,12,2 {
-					compatible = "pci8086,8817";
-					reg = <0x00026200 0 0 0 0>;
-
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					rtc@0x68 {
-						compatible = "st,m41t81s";
-						reg = <0x68>;
-					};
-				};
-			};
-		};
-	};
-
-	plat_regs: system-controller@17ffd000 {
-		compatible = "img,boston-platform-regs", "syscon";
-		reg = <0x17ffd000 0x1000>;
-		bootph-all;
-	};
-
-	clk_boston: clock {
-		compatible = "img,boston-clock";
-		#clock-cells = <1>;
-		regmap = <&plat_regs>;
-		bootph-all;
-	};
-
-	reboot: syscon-reboot {
-		compatible = "syscon-reboot";
-		regmap = <&plat_regs>;
-		offset = <0x10>;
-		mask = <0x10>;
-	};
-
-	uart0: uart@17ffe000 {
-		compatible = "ns16550a";
-		reg = <0x17ffe000 0x1000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
-
-		clocks = <&clk_boston BOSTON_CLK_SYS>;
-
-		bootph-all;
-	};
-
-	lcd: lcd@17fff000 {
-		compatible = "img,boston-lcd";
-		reg = <0x17fff000 0x8>;
-	};
-
-	flash@18000000 {
-		compatible = "cfi-flash";
-		reg = <0x18000000 0x8000000>;
-		bank-width = <2>;
-	};
-};
--- a/arch/mips/include/asm/acpi_table.h
+++ b/arch/mips/include/asm/acpi_table.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+/*
+ * This file is needed by some drivers.
+ */
+
+#endif /* __ASM_ACPI_TABLE_H__ */
--- a/board/imgtec/boston/Kconfig
+++ b/board/imgtec/boston/Kconfig
@@ -9,6 +9,10 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "boston"

+
+config ENV_SOURCE_FILE
+       default "boston"
+
 config TEXT_BASE
 	default 0x9fc00000 if 32BIT
 	default 0xffffffff9fc00000 if 64BIT
--- a/board/imgtec/boston/MAINTAINERS
+++ b/board/imgtec/boston/MAINTAINERS
@@ -1,6 +1,7 @@
 BOSTON BOARD
-M:	Paul Burton <paul.burton@mips.com>
+M:	Paul Burton <paulburton@kernel.org>
 S:	Maintained
+F:  arch/mips/dts/boston-u-boot.dtsi
 F:	board/imgtec/boston/
 F:	include/configs/boston.h
 F:	configs/boston32r2_defconfig
--- a/board/imgtec/boston/boston.env
+++ b/board/imgtec/boston/boston.env
@@ -0,0 +1,9 @@
+#ifdef CONFIG_64BIT
+fdt_addr_r=0xffffffff80001000
+kernel_addr_r=0xffffffff88000000
+ramdisk_addr_r=0xffffffff8b000000
+#else
+fdt_addr_r=0x80001000
+kernel_addr_r=0x88000000
+ramdisk_addr_r=0x8b000000
+#endif
--- a/board/imgtec/malta/MAINTAINERS
+++ b/board/imgtec/malta/MAINTAINERS
@@ -1,5 +1,5 @@
 MALTA BOARD
-M:	Paul Burton <paul.burton@mips.com>
+M:	Paul Burton <paulburton@kernel.org>
 S:	Maintained
 F:	board/imgtec/malta/
 F:	include/configs/malta.h
--- a/configs/boston32r2_defconfig
+++ b/configs/boston32r2_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x88000000
 CONFIG_ENV_ADDR=0xBFFE0000
--- a/configs/boston32r2el_defconfig
+++ b/configs/boston32r2el_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x88000000
 CONFIG_ENV_ADDR=0xBFFE0000
--- a/configs/boston32r6_defconfig
+++ b/configs/boston32r6_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x88000000
 CONFIG_ENV_ADDR=0xBFFE0000
--- a/configs/boston32r6el_defconfig
+++ b/configs/boston32r6el_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x88000000
 CONFIG_ENV_ADDR=0xBFFE0000
--- a/configs/boston64r2_defconfig
+++ b/configs/boston64r2_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
--- a/configs/boston64r2el_defconfig
+++ b/configs/boston64r2el_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
--- a/configs/boston64r6_defconfig
+++ b/configs/boston64r6_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
--- a/configs/boston64r6el_defconfig
+++ b/configs/boston64r6el_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_DEFAULT_DEVICE_TREE="img/boston"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0xffffffff88000000
 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -420,7 +420,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,

 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
 {
-	phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl);
+	phys_addr_t pa = virt_to_phys(pp->cmd_tbl);

 	pp->cmd_slot->opts = cpu_to_le32(opts);
 	pp->cmd_slot->status = 0;
@@ -449,7 +449,7 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 {
 	struct ahci_ioports *pp = &(uc_priv->port[port]);
 	void __iomem *port_mmio = pp->port_mmio;
-	u64 dma_addr;
+	phys_addr_t dma_addr;
 	u32 port_status;
 	void __iomem *mem;

@@ -472,34 +472,32 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 	 * First item in chunk of DMA memory: 32-slot command table,
 	 * 32 bytes each in size
 	 */
-	pp->cmd_slot =
-		(struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
-	debug("cmd_slot = %p\n", pp->cmd_slot);
-	mem += (AHCI_CMD_SLOT_SZ + 224);
+	pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
+	mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT;

 	/*
 	 * Second item: Received-FIS area
 	 */
-	pp->rx_fis = virt_to_phys((void *)mem);
+	pp->rx_fis = mem;
 	mem += AHCI_RX_FIS_SZ;

 	/*
 	 * Third item: data area for storing a single command
 	 * and its scatter-gather table
 	 */
-	pp->cmd_tbl = virt_to_phys((void *)mem);
-	debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
+	pp->cmd_tbl = mem;

 	mem += AHCI_CMD_TBL_HDR;
-	pp->cmd_tbl_sg =
-			(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
+	pp->cmd_tbl_sg = (struct ahci_sg *)(mem);

-	dma_addr = (ulong)pp->cmd_slot;
-	writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
-	writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
-	dma_addr = (ulong)pp->rx_fis;
-	writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
-	writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
+	dma_addr = virt_to_phys(pp->cmd_slot);
+	debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr);
+	writel_with_flush(lower_32_bits(dma_addr), port_mmio + PORT_LST_ADDR);
+	writel_with_flush(upper_32_bits(dma_addr), port_mmio + PORT_LST_ADDR_HI);
+	dma_addr = virt_to_phys(pp->rx_fis);
+	debug("rx_fis_dma = 0x%08llx\n", (u64)dma_addr);
+	writel_with_flush(lower_32_bits(dma_addr), port_mmio + PORT_FIS_ADDR);
+	writel_with_flush(upper_32_bits(dma_addr), port_mmio + PORT_FIS_ADDR_HI);

 #ifdef CONFIG_SUNXI_AHCI
 	sunxi_dma_init(port_mmio);
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -7,6 +7,7 @@
 #include <ahci.h>
 #include <blk.h>
 #include <bootdev.h>
+#include <clk.h>
 #include <cpu_func.h>
 #include <dm.h>
 #include <dwc_ahsata.h>
@@ -19,9 +20,11 @@
 #include <sata.h>
 #include <asm/cache.h>
 #include <asm/io.h>
+#if IS_ENABLED(CONFIG_ARCH_MX5) || IS_ENABLED(CONFIG_ARCH_MX6)
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/sata.h>
+#endif
 #include <linux/bitops.h>
 #include <linux/ctype.h>
 #include <linux/delay.h>
@@ -116,13 +119,12 @@ static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
 	return 0;
 }

-static int ahci_host_init(struct ahci_uc_priv *uc_priv)
+static int ahci_host_init(struct ahci_uc_priv *uc_priv, int clk)
 {
 	u32 tmp, cap_save, num_ports;
 	int i, j, timeout = 1000;
 	struct sata_port_regs *port_mmio = NULL;
 	struct sata_host_regs *host_mmio = uc_priv->mmio_base;
-	int clk = mxc_get_clock(MXC_SATA_CLK);

 	cap_save = readl(&host_mmio->cap);
 	cap_save |= SATA_HOST_CAP_SSS;
@@ -330,6 +332,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
 {
 	struct ahci_ioports *pp = &uc_priv->port[port];
 	struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
+	phys_addr_t pa = virt_to_phys(buf);
 	u32 sg_count, max_bytes;
 	int i;

@@ -341,9 +344,8 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
 	}

 	for (i = 0; i < sg_count; i++) {
-		ahci_sg->addr =
-			cpu_to_le32((u32)buf + i * max_bytes);
-		ahci_sg->addr_hi = 0;
+		ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
+		ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
 		ahci_sg->flags_size = cpu_to_le32(0x3fffff &
 					(buf_len < max_bytes
 					? (buf_len - 1)
@@ -359,14 +361,14 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
 {
 	struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
 					AHCI_CMD_SLOT_SZ * cmd_slot);
+	phys_addr_t pa = virt_to_phys(pp->cmd_tbl);

 	memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
 	cmd_hdr->opts = cpu_to_le32(opts);
 	cmd_hdr->status = 0;
-	pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
+	pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
 #ifdef CONFIG_PHYS_64BIT
-	pp->cmd_slot->tbl_addr_hi =
-	    cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
+	pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
 #endif
 }

@@ -404,7 +406,7 @@ static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
 	}
 	ahci_fill_cmd_slot(pp, cmd_slot, opts);

-	flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
+	flush_cache((ulong)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
 	writel_with_flush(1 << cmd_slot, &port_mmio->ci);

 	if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
@@ -412,8 +414,8 @@ static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
 		printf("timeout exit!\n");
 		return -1;
 	}
-	invalidate_dcache_range((int)(pp->cmd_slot),
-				(int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
+	invalidate_dcache_range((ulong)(pp->cmd_slot),
+				(ulong)(pp->cmd_slot) + AHCI_PORT_PRIV_DMA_SZ);
 	debug("ahci_exec_ata_cmd: %d byte transferred.\n",
 	      pp->cmd_slot->status);
 	if (!is_write)
@@ -441,8 +443,9 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 {
 	struct ahci_ioports *pp = &uc_priv->port[port];
 	struct sata_port_regs *port_mmio = pp->port_mmio;
+	phys_addr_t dma_addr;
 	u32 port_status;
-	u32 mem;
+	void *mem;
 	int timeout = 10000000;

 	debug("Enter start port: %d\n", port);
@@ -453,22 +456,20 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 		return -1;
 	}

-	mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
+	mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
 	if (!mem) {
 		printf("No mem for table!\n");
 		return -ENOMEM;
 	}

-	mem = (mem + 0x400) & (~0x3ff);	/* Aligned to 1024-bytes */
-	memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
+	memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);

 	/*
 	 * First item in chunk of DMA memory: 32-slot command table,
 	 * 32 bytes each in size
 	 */
 	pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
-	debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
-	mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
+	mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT;

 	/*
 	 * Second item: Received-FIS area, 256-Byte aligned
@@ -481,14 +482,19 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 	 * and its scatter-gather table
 	 */
 	pp->cmd_tbl = mem;
-	debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
-
 	mem += AHCI_CMD_TBL_HDR;
+	pp->cmd_tbl_sg = (struct ahci_sg *)mem;

 	writel_with_flush(0x00004444, &port_mmio->dmacr);
-	pp->cmd_tbl_sg = (struct ahci_sg *)mem;
-	writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
-	writel_with_flush(pp->rx_fis, &port_mmio->fb);
+	dma_addr = virt_to_phys(pp->cmd_slot);
+	debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr);
+	writel_with_flush(lower_32_bits(dma_addr), &port_mmio->clb);
+	writel_with_flush(upper_32_bits(dma_addr), &port_mmio->clbu);
+	dma_addr = virt_to_phys(pp->cmd_slot);
+	debug("rx_fis_slot_dma = 0x%08llx\n", (u64)dma_addr);
+	writel_with_flush(lower_32_bits(dma_addr), &port_mmio->fb);
+	writel_with_flush(upper_32_bits(dma_addr), &port_mmio->fbu);
+

 	/* Enable FRE */
 	writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
@@ -910,17 +916,41 @@ int dwc_ahsata_scan(struct udevice *dev)
 int dwc_ahsata_probe(struct udevice *dev)
 {
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct clk_bulk clk_bulk __maybe_unused;
+	struct clk clk __maybe_unused;
+	int sataclk;
 	int ret;

-#if defined(CONFIG_MX6)
+#if IS_ENABLED(CONFIG_MX6)
 	setup_sata();
 #endif
+#if IS_ENABLED(CONFIG_MX5) || IS_ENABLED(CONFIG_MX6)
+	sataclk = mxc_get_clock(MXC_SATA_CLK);
+#else
+	ret = clk_get_bulk(dev, &clk_bulk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&clk_bulk);
+	if (ret)
+		return ret;
+
+	ret	= clk_get_by_name(dev, "sata", &clk);
+	if (ret)
+		return ret;
+
+	sataclk = clk_get_rate(&clk);
+#endif
+	if (IS_ERR_VALUE(sataclk)) {
+		log_err("Unable to get SATA clock rate\n");
+		return -EINVAL;
+	}
 	uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 			ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
 	uc_priv->mmio_base = dev_read_addr_ptr(dev);

 	/* initialize adapter */
-	ret = ahci_host_init(uc_priv);
+	ret = ahci_host_init(uc_priv, sataclk);
 	if (ret)
 		return ret;

@@ -962,7 +992,6 @@ U_BOOT_DRIVER(dwc_ahsata_blk) = {
 	.ops		= &dwc_ahsata_blk_ops,
 };

-#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
 struct ahci_ops dwc_ahsata_ahci_ops = {
 	.port_status = dwc_ahsata_port_status,
 	.reset       = dwc_ahsata_bus_reset,
@@ -970,7 +999,9 @@ struct ahci_ops dwc_ahsata_ahci_ops = {
 };

 static const struct udevice_id dwc_ahsata_ahci_ids[] = {
+	{ .compatible = "fsl,imx53-ahci" },
 	{ .compatible = "fsl,imx6q-ahci" },
+	{ .compatible = "fsl,imx6qp-ahci" },
 	{ }
 };

@@ -981,4 +1012,3 @@ U_BOOT_DRIVER(dwc_ahsata_ahci) = {
 	.ops      = &dwc_ahsata_ahci_ops,
 	.probe    = dwc_ahsata_probe,
 };
-#endif
--- a/drivers/ata/dwc_ahsata_priv.h
+++ b/drivers/ata/dwc_ahsata_priv.h
@@ -7,8 +7,6 @@
 #ifndef __DWC_AHSATA_PRIV_H__
 #define __DWC_AHSATA_PRIV_H__

-#define DWC_AHSATA_MAX_CMD_SLOTS	32
-
 /* Max host controller numbers */
 #define SATA_HC_MAX_NUM		4
 /* Max command queue depth per host controller */
--- a/drivers/clk/clk_boston.c
+++ b/drivers/clk/clk_boston.c
@@ -58,17 +58,21 @@ const struct clk_ops clk_boston_ops = {
 	.get_rate = clk_boston_get_rate,
 };

-static int clk_boston_of_to_plat(struct udevice *dev)
+static int clk_boston_probe(struct udevice *dev)
 {
 	struct clk_boston *state = dev_get_plat(dev);
 	struct udevice *syscon;
 	int err;

-	err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
-					   "regmap", &syscon);
-	if (err) {
-		pr_err("unable to find syscon device\n");
-		return err;
+	if (dev->parent && device_get_uclass_id(dev->parent) == UCLASS_SYSCON) {
+		syscon = dev->parent;
+	} else {
+		err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+						   "regmap", &syscon);
+		if (err) {
+			pr_err("unable to find syscon device\n");
+			return err;
+		}
 	}

 	state->regmap = syscon_get_regmap(syscon);
@@ -91,7 +95,8 @@ U_BOOT_DRIVER(clk_boston) = {
 	.name = "boston_clock",
 	.id = UCLASS_CLK,
 	.of_match = clk_boston_match,
-	.of_to_plat = clk_boston_of_to_plat,
+	.probe = clk_boston_probe,
 	.plat_auto	= sizeof(struct clk_boston),
 	.ops = &clk_boston_ops,
+	.flags = DM_FLAG_PRE_RELOC,
 };
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -67,6 +67,7 @@ config PCI_CONFIG_HOST_BRIDGE
 config PCI_MAP_SYSTEM_MEMORY
 	bool "Map local system memory from a virtual base address"
 	depends on MIPS
+	default y if !ARCH_MAP_SYSMEM
 	help
 	  Say Y if base address of system memory is being used as a virtual address
 	  instead of a physical address (e.g. on MIPS). The PCI core will then remap
@@ -75,6 +76,15 @@ config PCI_MAP_SYSTEM_MEMORY
 	  This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still
 	  being used as virtual address.

+config PCI_BRIDGE_MEM_ALIGNMENT
+	hex "Alignment boundary of PCI memory resource allocation"
+	default 0x10000 if TARGET_BOSTON
+	default 0x100000
+	help
+	  Specify a boundary for alignment of PCI memory resource allocation,
+	  this is normally 0x100000 (1MB) but can be reduced to accommodate
+	  hardware with tight bridge range if hardware allows.
+
 config PCI_SRIOV
 	bool "Enable Single Root I/O Virtualization support for PCI"
 	help
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -373,8 +373,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
 	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);

 	if (pci_mem) {
-		/* Round memory allocator to 1MB boundary */
-		pciauto_region_align(pci_mem, 0x100000);
+		/* Round memory allocator */
+		pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);

 		/*
 		 * Set up memory and I/O filter limits, assume 32-bit
@@ -388,8 +388,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
 	}

 	if (pci_prefetch) {
-		/* Round memory allocator to 1MB boundary */
-		pciauto_region_align(pci_prefetch, 0x100000);
+		/* Round memory allocator */
+		pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);

 		/*
 		 * Set up memory and I/O filter limits, assume 32-bit
@@ -466,8 +466,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
 	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));

 	if (pci_mem) {
-		/* Round memory allocator to 1MB boundary */
-		pciauto_region_align(pci_mem, 0x100000);
+		/* Round memory allocator */
+		pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);

 		dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
 				      ((pci_mem->bus_lower - 1) >> 16) &
@@ -481,8 +481,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
 				     &prefechable_64);
 		prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;

-		/* Round memory allocator to 1MB boundary */
-		pciauto_region_align(pci_prefetch, 0x100000);
+		/* Round memory allocator */
+		pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);

 		dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
 				      (((pci_prefetch->bus_lower - 1) >> 16) &
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -18,14 +18,19 @@
 */
 struct xilinx_pcie {
 	void *cfg_base;
+	pci_size_t size;
+	int first_busno;
 };

 /* Register definitions */
-#define XILINX_PCIE_REG_PSCR		0x144
-#define XILINX_PCIE_REG_PSCR_LNKUP	BIT(11)
-#define XILINX_PCIE_REG_RPSC		0x148
-#define XILINX_PCIE_REG_RPSC_BEN	BIT(0)
-
+#define XILINX_PCIE_REG_BRIDGE_INFO			0x130
+#define  XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_SHIFT	16
+#define  XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_MASK	(0x7 << 16)
+#define XILINX_PCIE_REG_INT_MASK			0x13c
+#define XILINX_PCIE_REG_PSCR				0x144
+#define  XILINX_PCIE_REG_PSCR_LNKUP			BIT(11)
+#define XILINX_PCIE_REG_RPSC				0x148
+#define  XILINX_PCIE_REG_RPSC_BEN			BIT(0)
 /**
 * pcie_xilinx_link_up() - Check whether the PCIe link is up
 * @pcie: Pointer to the PCI controller state
@@ -61,14 +66,18 @@ static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf,
 				      uint offset, void **paddress)
 {
 	struct xilinx_pcie *pcie = dev_get_priv(udev);
-	unsigned int bus = PCI_BUS(bdf);
+	unsigned int bus = PCI_BUS(bdf) - pcie->first_busno;
 	unsigned int dev = PCI_DEV(bdf);
 	unsigned int func = PCI_FUNC(bdf);
+	int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
 	void *addr;

 	if ((bus > 0) && !pcie_xilinx_link_up(pcie))
 		return -ENODEV;

+	if (bus > num_buses)
+		return -ENODEV;
+
 	/*
 	 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
 	 * limited to a single device each.
@@ -142,20 +151,37 @@ static int pcie_xilinx_of_to_plat(struct udevice *dev)
 	struct xilinx_pcie *pcie = dev_get_priv(dev);
 	fdt_addr_t addr;
 	fdt_size_t size;
-	u32 rpsc;

 	addr = dev_read_addr_size(dev, &size);
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;

-	pcie->cfg_base = devm_ioremap(dev, addr, size);
-	if (IS_ERR(pcie->cfg_base))
-		return PTR_ERR(pcie->cfg_base);
+	pcie->cfg_base = map_physmem(addr, size, MAP_NOCACHE);
+	if (!pcie->cfg_base)
+		return -ENOMEM;
+	pcie->size = size;
+	return 0;
+}

-	/* Enable the Bridge enable bit */
-	rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+static int pci_xilinx_probe(struct udevice *dev)
+{
+	struct xilinx_pcie *pcie = dev_get_priv(dev);
+	u32 rpsc;
+	int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+	pcie->first_busno = dev_seq(dev);
+
+	/* Disable all interrupts */
+	writel(0, pcie->cfg_base + XILINX_PCIE_REG_INT_MASK);
+
+	/* Enable the bridge */
+	rpsc = readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
 	rpsc |= XILINX_PCIE_REG_RPSC_BEN;
-	__raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+	writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+
+	/* Enable access to all possible subordinate buses */
+	writel((0 << 0) | (1 << 8) | (num_buses << 16),
+	       pcie->cfg_base + PCI_PRIMARY_BUS);

 	return 0;
 }
@@ -176,5 +202,6 @@ U_BOOT_DRIVER(pcie_xilinx) = {
 	.of_match		= pcie_xilinx_ids,
 	.ops			= &pcie_xilinx_ops,
 	.of_to_plat	= pcie_xilinx_of_to_plat,
+	.probe			= pci_xilinx_probe,
 	.priv_auto	= sizeof(struct xilinx_pcie),
 };
--- a/dts/upstream/src/mips/Makefile
+++ b/dts/upstream/src/mips/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/scripts/Makefile.dts
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS += -a 0x8
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := */*.dtb */*.dtbo
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -137,8 +137,8 @@ struct ahci_ioports {
 	void __iomem	*port_mmio;
 	struct ahci_cmd_hdr	*cmd_slot;
 	struct ahci_sg		*cmd_tbl_sg;
-	ulong	cmd_tbl;
-	u32	rx_fis;
+	void *cmd_tbl;
+	void *rx_fis;
 };

 /**