Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra

arch/arm/dts/Makefile

@@ -87,6 +87,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
 	tegra20-asus-tf101g.dtb \
 	tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
+	tegra20-motorola-daytona.dtb \
+	tegra20-motorola-olympus.dtb \
 	tegra20-paz00.dtb \
 	tegra20-plutux.dtb \
 	tegra20-seaboard.dtb \
@@ -116,7 +118,9 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
 	tegra30-ouya.dtb \
 	tegra30-tec-ng.dtb \
 	tegra30-wexler-qc750.dtb \
+	tegra114-asus-tf701t.dtb \
 	tegra114-dalmore.dtb \
+	tegra114-nvidia-tegratab.dtb \
 	tegra124-apalis.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-nyan-big.dtb \

arch/arm/dts/tegra20-motorola-daytona.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra20-motorola-mot.dtsi"
+
+/ {
+	model = "Motorola Droid X2 (MB870)";
+	compatible = "motorola,daytona", "nvidia,tegra20";
+};

arch/arm/dts/tegra20-motorola-mot.dtsi

@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/input.h>
+#include "tegra20.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uartb;
+	};
+
+	aliases {
+		i2c0 = &gen1_i2c;
+
+		spi0 = &cpcap_spi;
+
+		mmc0 = &sdmmc4;	/* eMMC */
+		mmc1 = &sdmmc3; /* uSD slot */
+
+		rtc1 = "/rtc@7000e000";
+
+		usb0 = &micro_usb;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	host1x@50000000 {
+		dsia: dsi@54300000 {
+			clocks = <&tegra_car TEGRA20_CLK_DSI>,
+				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+			clock-names = "dsi", "parent";
+			status = "okay";
+
+			avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+
+			panel {
+				compatible = "motorola,mot-panel";
+
+				reset-gpios = <&gpio TEGRA_GPIO(E, 3) GPIO_ACTIVE_LOW>;
+
+				vdd-supply = <&vdd_5v0_panel>;
+				vddio-supply = <&vdd_1v8_vio>;
+
+				backlight = <&backlight>;
+			};
+		};
+	};
+
+	gpio@6000d000 {
+		volume-buttons-hog {
+			gpio-hog;
+			gpios = <TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
+			output-low;
+		};
+
+		usb-mux-hog {
+			gpio-hog;
+			gpios = <TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>;
+			output-high;
+		};
+	};
+
+	pinmux@70000014 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			crt {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+
+			displaya {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld3",
+					      "ld5", "ld6", "ld7", "ld8",
+					      "ld9", "ld12", "ld13", "ld14",
+					      "ld15", "ld16", "ld17", "ldi",
+					      "lhp0", "lhp1", "lhp2", "lhs",
+					      "lpp", "lsc0", "lpw1", "lsda",
+					      "lspi";
+				nvidia,function = "displaya";
+			};
+
+			gmi {
+				nvidia,pins = "ata", "atc", "atd", "ate",
+					      "gmb", "gmd", "gpu";
+				nvidia,function = "gmi";
+			};
+
+			hdmi {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+			};
+
+			i2c1 {
+				nvidia,pins = "i2cp", "rm";
+				nvidia,function = "i2c1";
+			};
+
+			i2c2 {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+
+			i2c3 {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+
+			kbc {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					      "kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+
+			osc {
+				nvidia,pins = "cdev1", "cdev2";
+				nvidia,function = "osc";
+			};
+
+			owr {
+				nvidia,pins = "owc", "uac";
+				nvidia,function = "owr";
+			};
+
+			pcie {
+				nvidia,pins = "gpv";
+				nvidia,function = "pcie";
+			};
+
+			pwr-on {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+
+			rsvd4 {
+				nvidia,pins = "lvp0", "lvp1", "lvs", "lsc0",
+					      "ld10", "ld11", "lm1", "ld2",
+					      "ld4", "ldc";
+				nvidia,function = "rsvd4";
+			};
+
+			rtck {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+
+			sdio3 {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "sdio3";
+			};
+
+			sdio4 {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+
+			spdif {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+
+			spi1 {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+
+			spi2 {
+				nvidia,pins = "spia", "spib", "spic", "spig",
+					      "spih";
+				nvidia,function = "spi2";
+			};
+
+			spi3 {
+				nvidia,pins = "lm0", "lpw0", "lpw2", "lsc1";
+				nvidia,function = "spi3";
+			};
+
+			uarta {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uarta";
+			};
+
+			uartc {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+
+			uartd {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+
+			ulpi {
+				nvidia,pins = "uab";
+				nvidia,function = "ulpi";
+			};
+
+			vi {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd",
+					      "dte";
+				nvidia,function = "vi";
+			};
+
+			vi-sensor-clk {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+
+			conf-lcsn {
+				nvidia,pins = "lcsn", "lpw1", "lsck", "lsda",
+					      "lsdi", "ldc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+
+			conf-ata {
+				nvidia,pins = "ata", "atb", "atc", "ddc",
+					      "gmc", "gpu", "kbca", "kbcb",
+					      "kbcc", "kbcd", "kbce", "kbcf",
+					      "lm1", "lvp0", "owc", "sdb",
+					      "sdc", "sdd", "sdio1", "uaa",
+					      "uad", "uca", "ucb", "pmce",
+					      "lvs";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf-cdev1 {
+				nvidia,pins = "cdev1", "crtp", "csus", "pta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			};
+
+			conf-atd {
+				nvidia,pins = "atd", "ate", "cdev2", "dte",
+					      "gma", "gmb", "gmd", "gme",
+					      "gpu7", "gpv", "hdint", "i2cp",
+					      "irrx", "irtx", "pmc", "rm",
+					      "slxa",	"slxc", "slxd", "slxk",
+					      "spdi", "spdo", "spid", "spie",
+					      "spif", "uda", "ck32", "ddrc",
+					      "pmca", "pmcb", "pmcc", "pmcd",
+					      "xm2c", "xm2d";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf-ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+					      "ld4", "ld5", "ld6", "ld7",
+					      "ld8", "ld9", "ld10", "ld11",
+					      "ld12", "ld13", "ld14", "ld15",
+					      "ld16", "ld17", "ldi", "lhp0",
+					      "lhp1", "lhp2", "lhs", "lm0",
+					      "lpp", "lpw0", "lpw2", "lsc0",
+					      "lsc1", "lspi", "lvp1";
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf-dap1 {
+				nvidia,pins = "dap1", "dap2", "dap3", "dap4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+			};
+
+			conf-dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd",
+					      "dtf";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf-spi2 {
+				nvidia,pins = "spia", "spib", "spic", "spig",
+					      "spih";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+		};
+	};
+
+	uartb: serial@70006040 {
+		clocks = <&tegra_car 7>;
+		status = "okay";
+	};
+
+	gen1_i2c: i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		backlight: led-controller@38 {
+			compatible = "ti,lm3532";
+			reg = <0x38>;
+
+			enable-gpios = <&gpio TEGRA_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			backlight_led: led@0 {
+				reg = <0>;
+
+				led-sources = <2>;
+				led-max-microamp = <26600>;
+
+				ti,led-mode = <0>;
+				ti,linear-mapping-mode;
+
+				label = ":backlight";
+			};
+		};
+	};
+
+	cpcap_spi: spi@7000d600 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+
+		pmic: cpcap@0 {
+			compatible = "motorola,cpcap";
+			reg = <0>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			spi-cs-high;
+			spi-max-frequency = <8000000>;
+
+			power_button: button {
+				compatible = "motorola,cpcap-pwrbutton";
+
+				interrupt-parent = <&pmic>;
+				interrupts = <23 IRQ_TYPE_NONE>;
+
+				linux,code = <KEY_ENTER>;
+			};
+
+			regulator {
+				compatible = "motorola,mot-cpcap-regulator";
+
+				regulators {
+					/* SW1 is vdd_cpu */
+					/* SW2 is vdd_core */
+
+					vdd_1v8_vio: sw3 {
+						regulator-name = "vdd_1v8_vio";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					/* SW4 is vdd_aon (rtc) */
+
+					vcore_emmc: vsdio {
+						regulator-name = "vcore_emmc";
+						regulator-min-microvolt = <3000000>;
+						regulator-max-microvolt = <3000000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					avdd_dsi_csi: vcsi {
+						regulator-name = "avdd_dsi_csi";
+						regulator-min-microvolt = <1200000>;
+						regulator-max-microvolt = <1200000>;
+						regulator-boot-on;
+					};
+
+					vddio_usd: vsimcard {
+						regulator-name = "vddio_usd";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <2900000>;
+						regulator-boot-on;
+					};
+
+					avdd_3v3_periph: vusb {
+						regulator-name = "avdd_usb";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+				};
+			};
+		};
+	};
+
+	micro_usb: usb@c5000000 {
+		status = "okay";
+		dr_mode = "otg";
+	};
+
+	usb-phy@c5000000 {
+		status = "okay";
+		vbus-supply = <&avdd_3v3_periph>;
+	};
+
+	sdmmc3: sdhci@c8000400 {
+		status = "okay";
+		bus-width = <4>;
+
+		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+
+		vmmc-supply = <&vdd_usd>;
+		vqmmc-supply = <&vddio_usd>;
+	};
+
+	sdmmc4: sdhci@c8000600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+
+		vmmc-supply = <&vcore_emmc>;
+		vqmmc-supply = <&vdd_1v8_vio>;
+	};
+
+	/* 32KHz oscillator which is used by PMC */
+	clk32k_in: clock-32k-in {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "ref-oscillator";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-volume-down {
+			label = "Volume Down";
+			gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_DOWN>;
+		};
+
+		key-volume-up {
+			label = "Volume Up";
+			gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_UP>;
+		};
+	};
+
+	gpio-poweroff {
+		compatible = "gpio-poweroff";
+		gpios = <&gpio TEGRA_GPIO(V, 7) GPIO_ACTIVE_LOW>;
+		timeout-ms = <500>;
+	};
+
+	vdd_5v0_panel: regulator-panel {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_5v0_disp";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio TEGRA_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vdd_usd: regulator-usd {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usd";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&gpio TEGRA_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};

arch/arm/dts/tegra20-motorola-olympus.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra20-motorola-mot.dtsi"
+
+/ {
+	model = "Motorola Atrix 4G (MB860)";
+	compatible = "motorola,olympus", "nvidia,tegra20";
+};

arch/arm/include/asm/arch-tegra20/funcmux.h

@@ -19,6 +19,7 @@ enum {
 	FUNCMUX_UART1_UAA_UAB,
 	FUNCMUX_UART1_GPU,
 	FUNCMUX_UART1_SDIO1,
+	FUNCMUX_UART1_SDB_SDD,
 	FUNCMUX_UART2_UAD = 0,
 	FUNCMUX_UART4_GMC = 0,
 

arch/arm/mach-tegra/board.c

@@ -169,6 +169,8 @@ static int uart_configs[] = {
 	FUNCMUX_UART1_GPU,
  #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
 	FUNCMUX_UART1_SDIO1,
+ #elif defined(CONFIG_TEGRA_UARTA_SDB_SDD)
+	FUNCMUX_UART1_SDB_SDD,
  #else
 	FUNCMUX_UART1_IRRX_IRTX,
 #endif
@@ -236,18 +238,23 @@ void board_init_uart_f(void)
 	int uart_ids = 0;	/* bit mask of which UART ids to enable */
 
 #ifdef CONFIG_TEGRA_ENABLE_UARTA
+#define CFG_SYS_NS16550_COM1	NV_PA_APB_UARTA_BASE
 	uart_ids |= UARTA;
 #endif
 #ifdef CONFIG_TEGRA_ENABLE_UARTB
+#define CFG_SYS_NS16550_COM1	NV_PA_APB_UARTB_BASE
 	uart_ids |= UARTB;
 #endif
 #ifdef CONFIG_TEGRA_ENABLE_UARTC
+#define CFG_SYS_NS16550_COM1	NV_PA_APB_UARTC_BASE
 	uart_ids |= UARTC;
 #endif
 #ifdef CONFIG_TEGRA_ENABLE_UARTD
+#define CFG_SYS_NS16550_COM1	NV_PA_APB_UARTD_BASE
 	uart_ids |= UARTD;
 #endif
 #ifdef CONFIG_TEGRA_ENABLE_UARTE
+#define CFG_SYS_NS16550_COM1	NV_PA_APB_UARTE_BASE
 	uart_ids |= UARTE;
 #endif
 	setup_uarts(uart_ids);

arch/arm/mach-tegra/board2.c

@@ -96,7 +96,7 @@ int checkboard(void)
 {
 	int board_id = tegra_board_id();
 
-	printf("Board: %s", CFG_TEGRA_BOARD_STRING);
+	printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
 	if (board_id != -1)
 		printf(", ID: %d\n", board_id);
 	printf("\n");

arch/arm/mach-tegra/clock.c

@@ -703,6 +703,12 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
 	else
 		writel(base_reg, &simple_pll->pll_base);
 
+	/* PLLD and PLLD2 are only clocks which have ENABLE bit */
+	if (clkid == CLOCK_ID_DISPLAY)
+		setbits_le32(&pll->pll_misc, BIT(PLLD_CLKENABLE));
+	if (clkid == CLOCK_ID_DISPLAY2)
+		setbits_le32(&simple_pll->pll_misc, BIT(PLLD_CLKENABLE));
+
 	/*
 	 * Changing clocks was never intended in the U-Boot for Tegra.
 	 * If a clock is changed after clock_init() the parent rate is wrong.

arch/arm/mach-tegra/tegra114/Kconfig

@@ -8,11 +8,21 @@ config TARGET_DALMORE
 	bool "NVIDIA Tegra114 Dalmore evaluation board"
 	select BOARD_LATE_INIT
 
+config TARGET_TEGRATAB
+	bool "NVIDIA Tegra114 TegraTab evaluation board"
+	select BOARD_LATE_INIT
+
+config TARGET_TRANSFORMER_T114
+	bool "ASUS Tegra114 Transformer board"
+	select BOARD_LATE_INIT
+
 endchoice
 
 config SYS_SOC
 	default "tegra114"
 
 source "board/nvidia/dalmore/Kconfig"
+source "board/nvidia/tegratab/Kconfig"
+source "board/asus/transformer-t114/Kconfig"
 
 endif

arch/arm/mach-tegra/tegra114/clock.c

@@ -796,7 +796,6 @@ struct periph_clk_init periph_clk_init_table[] = {
 	{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
 	{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },

arch/arm/mach-tegra/tegra124/clock.c

@@ -598,8 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
 	  .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },	/* PLLE */
 	{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
 	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLS (RESERVED) */
-	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
-	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLD2 */
+	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
+	  .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },	/* PLLD2 */
 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20,  .p_mask = 0xF,
 	  .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },	/* PLLDP */
 };

arch/arm/mach-tegra/tegra20/Kconfig

@@ -17,6 +17,9 @@ config TEGRA_UARTA_GPU
 config TEGRA_UARTA_SDIO1
 	bool
 
+config TEGRA_UARTA_SDB_SDD
+	bool
+
 choice
 	prompt "Tegra20 board select"
 	optional
@@ -29,6 +32,10 @@ config TARGET_MEDCOM_WIDE
 	bool "Avionic Design Medcom-Wide board"
 	select BOARD_LATE_INIT
 
+config TARGET_MOT
+	bool "Motorola Tegra20 board"
+	select BOARD_LATE_INIT
+
 config TARGET_PAZ00
 	bool "Paz00 board"
 	select BOARD_LATE_INIT
@@ -76,6 +83,7 @@ config SYS_SOC
 
 source "board/nvidia/harmony/Kconfig"
 source "board/avionic-design/medcom-wide/Kconfig"
+source "board/motorola/mot/Kconfig"
 source "board/compal/paz00/Kconfig"
 source "board/acer/picasso/Kconfig"
 source "board/avionic-design/plutux/Kconfig"

arch/arm/mach-tegra/tegra210/clock.c

@@ -668,8 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
 	  .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },	/* PLLE */
 	{ .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
 	  .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 },	/* PLLS (gone)*/
-	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
-	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLD2 */
+	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
+	  .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },	/* PLLD2 */
 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 19,  .p_mask = 0x1F,
 	  .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },	/* PLLDP */
 };

board/acer/picasso/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "acer"
 
 config SYS_CONFIG_NAME
-	default "picasso"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Acer Iconia Tab A500"
 
 endif

board/asus/grouper/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "asus"
 
 config SYS_CONFIG_NAME
-	default "grouper"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "ASUS Google Nexus 7 (2012)"
 
 endif

board/asus/transformer-t114/Kconfig

@@ -0,0 +1,16 @@
+if TARGET_TRANSFORMER_T114
+
+config SYS_BOARD
+	default "transformer-t114"
+
+config SYS_VENDOR
+	default "asus"
+
+config SYS_CONFIG_NAME
+	default "transformer-t114"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "ASUS Transformer T114"
+
+endif

board/asus/transformer-t114/MAINTAINERS

@@ -0,0 +1,8 @@
+TRANSFORMER T114 BOARD
+M:	Svyatoslav Ryhel <clamor95@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/tegra114-asus-tf701t.dts
+F:	board/asus/transformer-t114/
+F:	configs/tf701t_defconfig
+F:	doc/board/asus/transformer_t114.rst
+F:	include/configs/transformer-t114.h

board/asus/transformer-t114/Makefile

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com>
+#
+
+obj-$(CONFIG_XPL_BUILD) += transformer-t114-spl.o
+
+obj-y += transformer-t114.o

board/asus/transformer-t114/transformer-t114-spl.c

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  T114 Transformers SPL stage configuration
+ *
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2023
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65913_I2C_ADDR		(0x58 << 1)
+
+#define TPS65913_SMPS12_CTRL		0x20
+#define TPS65913_SMPS12_VOLTAGE		0x23
+#define TPS65913_SMPS45_CTRL		0x28
+#define TPS65913_SMPS45_VOLTAGE		0x2B
+
+#define TPS65913_SMPS12_CTRL_DATA	(0x5100 | TPS65913_SMPS12_CTRL)
+#define TPS65913_SMPS12_VOLTAGE_DATA	(0x3900 | TPS65913_SMPS12_VOLTAGE)
+#define TPS65913_SMPS45_CTRL_DATA	(0x5100 | TPS65913_SMPS45_CTRL)
+#define TPS65913_SMPS45_VOLTAGE_DATA	(0x4c00 | TPS65913_SMPS45_VOLTAGE)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set CORE VDD to 1.200V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA);
+
+	udelay(1000);
+
+	/* Set CPU VDD to 1.0125V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA);
+	udelay(10 * 1000);
+}

board/asus/transformer-t114/transformer-t114.c

@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2023
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+/* T114 Transformers derive from Macallan board */
+
+#include <dm.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+
+#define TPS65913_I2C_ADDRESS			0x58
+#define TPS65913_PRIMARY_SECONDARY_PAD2		0xfb
+#define   GPIO_4				BIT(0)
+#define TPS65913_PRIMARY_SECONDARY_PAD3		0xfe
+#define   DVFS2					BIT(1)
+#define   DVFS1					BIT(0)
+
+/* We are using this function only till palmas pinctrl driver is available */
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev);
+	if (ret) {
+		log_debug("%s: cannot find PMIC I2C chip\n", __func__);
+		return;
+	}
+
+	/* GPIO4 function has to be GPIO */
+	dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2,
+			  GPIO_4, 0);
+
+	/* DVFS1 is enabled, DVFS2 is disabled */
+	dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3,
+			  DVFS2 | DVFS1, DVFS1);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* Remove TrustZone nodes */
+	fdt_del_node_and_alias(blob, "/firmware");
+	fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+	return 0;
+}
+#endif

board/asus/transformer-t114/transformer-t114.env

@@ -0,0 +1,15 @@
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Hall Sensor
+button_cmd_1=poweroff
+
+fastboot_partition_alias_boot=CAC
+fastboot_partition_alias_root=UDA
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:e; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1

board/asus/transformer-t20/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "asus"
 
 config SYS_CONFIG_NAME
-	default "transformer-t20"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "ASUS Transformer T20"
 
 endif

board/asus/transformer-t30/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "asus"
 
 config SYS_CONFIG_NAME
-	default "transformer-t30"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "ASUS Transformer T30"
 
 endif

board/avionic-design/medcom-wide/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "avionic-design"
 
 config SYS_CONFIG_NAME
-	default "medcom-wide"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Avionic Design Medcom-Wide"
 
 endif

board/avionic-design/plutux/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "avionic-design"
 
 config SYS_CONFIG_NAME
-	default "plutux"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Avionic Design Plutux"
 
 endif

board/avionic-design/tec-ng/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "avionic-design"
 
 config SYS_CONFIG_NAME
-	default "tec-ng"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Avionic Design Tamonten™ NG Evaluation Carrier"
 
 endif

board/avionic-design/tec/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "avionic-design"
 
 config SYS_CONFIG_NAME
-	default "tec"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Avionic Design Tamonten Evaluation Carrier"
 
 endif

board/cei/cei-tk1-som/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "cei"
 
 config SYS_CONFIG_NAME
-	default "cei-tk1-som"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "CEI tk1-som"
 
 endif

board/compal/paz00/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "compal"
 
 config SYS_CONFIG_NAME
-	default "paz00"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Compal Paz00"
 
 endif

board/compulab/trimslice/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "compulab"
 
 config SYS_CONFIG_NAME
-	default "trimslice"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Compulab Trimslice"
 
 endif

board/htc/endeavoru/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "htc"
 
 config SYS_CONFIG_NAME
-	default "endeavoru"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "HTC One X"
 
 endif

board/lenovo/ideapad-yoga-11/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "lenovo"
 
 config SYS_CONFIG_NAME
-	default "ideapad-yoga-11"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Lenovo Ideapad Yoga 11"
 
 endif

board/lg/x3-t30/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "lg"
 
 config SYS_CONFIG_NAME
-	default "x3-t30"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "LG X3 Board"
 
 endif

board/microsoft/surface-rt/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "microsoft"
 
 config SYS_CONFIG_NAME
-	default "surface-rt"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Microsoft Surface RT"
 
 endif

board/motorola/mot/Kconfig

@@ -0,0 +1,16 @@
+if TARGET_MOT
+
+config SYS_BOARD
+	default "mot"
+
+config SYS_VENDOR
+	default "motorola"
+
+config SYS_CONFIG_NAME
+	default "mot"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Motorola Mot"
+
+endif

board/motorola/mot/MAINTAINERS

@@ -0,0 +1,7 @@
+MOT BOARD
+M:	Svyatoslav Ryhel <clamor95@gmail.com>
+S:	Maintained
+F:	board/motorola/mot/
+F:	configs/mot_defconfig
+F:	doc/board/motorola/mot.rst
+F:	include/configs/mot.h

board/motorola/mot/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#  (C) Copyright 2025
+#  Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_XPL_BUILD) += mot-spl.o

board/motorola/mot/configs/daytona.config

@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-daytona"
+CONFIG_SYS_PROMPT="Tegra20 (Daytona) # "

board/motorola/mot/configs/olympus.config

@@ -0,0 +1,2 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus"
+CONFIG_SYS_PROMPT="Tegra20 (Olympus) # "

board/motorola/mot/mot-spl.c

@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  T20 Motorola Atrix 4G and Droid X2 SPL stage configuration
+ *
+ *  (C) Copyright 2025
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
+#include <spl_gpio.h>
+#include <linux/delay.h>
+
+/*
+ * Unlike all other supported Tegra devices and most known Tegra devices, the
+ * both Atrix 4G and Droid X2 have no hardware way to enter APX/RCM mode, which
+ * may lead to a dangerous situation when, if BCT is set correctly and the
+ * bootloader is faulty, the device will hang in a permanent brick state.
+ * Exiting from this state can be done only by disassembling the device and
+ * shortening testpad to the ground.
+ *
+ * To prevent this or to minimize the probability of such an accident, it was
+ * proposed to add the RCM rebooting hook as early into SPL as possible since
+ * SPL is much more robust and has minimal changes that can break bootflow.
+ *
+ * gpio_early_init_uart() function was chosen as it is the earliest function
+ * exposed for setup by the device. Hook performs a check for volume up
+ * button state and triggers RCM if it is pressed.
+ */
+void gpio_early_init_uart(void)
+{
+	int value;
+
+	/* Configure pinmux for PR0 */
+	pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_KBC);
+	pinmux_set_pullupdown(PMUX_PINGRP_KBCA, PMUX_PULL_UP);
+	pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+
+	/* Configure pinmux for PQ0 */
+	pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_KBC);
+	pinmux_set_pullupdown(PMUX_PINGRP_KBCC, PMUX_PULL_UP);
+	pinmux_tristate_disable(PMUX_PINGRP_KBCC);
+
+	/* Hog column 0 (PQ0) low - active */
+	spl_gpio_output(NULL, TEGRA_GPIO(Q, 0), 0);
+	udelay(500);
+
+	spl_gpio_input(NULL, TEGRA_GPIO(R, 0));
+	value = spl_gpio_get_value(NULL, TEGRA_GPIO(R, 0));
+
+	/* Enter RCM if button is pressed */
+	if (!value) {
+		tegra_pmc_writel(2, PMC_SCRATCH0);
+		tegra_pmc_writel(PMC_CNTRL_MAIN_RST, PMC_CNTRL);
+	}
+}

board/motorola/mot/mot.env

@@ -0,0 +1,15 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1

board/nvidia/beaver/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "beaver"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA Beaver"
 
 endif

board/nvidia/cardhu/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "cardhu"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA Cardhu"
 
 endif

board/nvidia/dalmore/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "dalmore"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA Dalmore"
 
 endif

board/nvidia/harmony/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "harmony"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA Harmony"
 
 endif

board/nvidia/jetson-tk1/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "jetson-tk1"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA Jetson TK1"
 
 endif

board/nvidia/nyan-big/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "nyan-big"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Google/NVIDIA Nyan-big"
 
 endif

board/nvidia/p2371-0000/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "p2371-0000"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA P2371-0000"
 
 endif

board/nvidia/p2371-2180/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "p2371-2180"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA P2371-2180"
 
 endif

board/nvidia/p2571/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "p2571"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA P2571"
 
 endif

board/nvidia/p2771-0000/Kconfig

@@ -11,6 +11,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "p2771-0000"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA P2771-0000"
 
 endif

board/nvidia/p3450-0000/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "p3450-0000"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA P3450-0000"
 
 endif

board/nvidia/seaboard/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "seaboard"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA Seaboard"
 
 endif

board/nvidia/tegratab/Kconfig

@@ -0,0 +1,16 @@
+if TARGET_TEGRATAB
+
+config SYS_BOARD
+	default "tegratab"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "tegratab"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA TegraTab"
+
+endif

board/nvidia/tegratab/MAINTAINERS

@@ -0,0 +1,8 @@
+TEGRATAB BOARD
+M:	Svyatoslav Ryhel <clamor95@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/tegra114-nvidia-tegratab.dts
+F:	board/nvidia/tegratab/
+F:	configs/tegratab_defconfig
+F:	doc/board/nvidia/tegratab.rst
+F:	include/configs/tegratab.h

board/nvidia/tegratab/Makefile

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com>
+#
+
+obj-$(CONFIG_XPL_BUILD) += tegratab-spl.o
+
+obj-y += tegratab.o

board/nvidia/tegratab/tegratab-spl.c

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  TegraTab SPL stage configuration
+ *
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2023
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65913_I2C_ADDR		(0x58 << 1)
+
+#define TPS65913_SMPS12_CTRL		0x20
+#define TPS65913_SMPS12_VOLTAGE		0x23
+#define TPS65913_SMPS45_CTRL		0x28
+#define TPS65913_SMPS45_VOLTAGE		0x2B
+
+#define TPS65913_SMPS12_CTRL_DATA	(0x5100 | TPS65913_SMPS12_CTRL)
+#define TPS65913_SMPS12_VOLTAGE_DATA	(0x3900 | TPS65913_SMPS12_VOLTAGE)
+#define TPS65913_SMPS45_CTRL_DATA	(0x5100 | TPS65913_SMPS45_CTRL)
+#define TPS65913_SMPS45_VOLTAGE_DATA	(0x4c00 | TPS65913_SMPS45_VOLTAGE)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set CORE VDD to 1.200V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA);
+
+	udelay(1000);
+
+	/* Set CPU VDD to 1.0125V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA);
+	udelay(10 * 1000);
+}

board/nvidia/tegratab/tegratab.c

@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2023
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+
+#define TPS65913_I2C_ADDRESS			0x58
+#define TPS65913_PRIMARY_SECONDARY_PAD2		0xfb
+#define   GPIO_4				BIT(0)
+#define TPS65913_PRIMARY_SECONDARY_PAD3		0xfe
+#define   DVFS2					BIT(1)
+#define   DVFS1					BIT(0)
+
+/* We are using this function only till palmas pinctrl driver is available */
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev);
+	if (ret) {
+		log_debug("%s: cannot find PMIC I2C chip\n", __func__);
+		return;
+	}
+
+	/* GPIO4 function has to be GPIO */
+	dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2,
+			  GPIO_4, 0);
+
+	/* DVFS1 is enabled, DVFS2 is disabled */
+	dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3,
+			  DVFS2 | DVFS1, DVFS1);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* Remove TrustZone nodes and memory reserves */
+	fdt_del_node_and_alias(blob, "/firmware");
+	fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+	fdt_del_node_and_alias(blob, "/reserved-memory/bootloader-firmware@b7e00000");
+
+	return 0;
+}
+#endif

board/nvidia/tegratab/tegratab.env

@@ -0,0 +1,15 @@
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Hall Sensor
+button_cmd_1=poweroff
+
+fastboot_partition_alias_boot=CAC
+fastboot_partition_alias_root=UDA
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:c; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1

board/nvidia/venice2/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "venice2"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA Venice2"
 
 endif

board/nvidia/ventana/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "nvidia"
 
 config SYS_CONFIG_NAME
-	default "ventana"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "NVIDIA Ventana"
 
 endif

board/ouya/ouya/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "ouya"
 
 config SYS_CONFIG_NAME
-	default "ouya"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Ouya Game Console"
 
 endif

board/sifive/unleashed/Kconfig

@@ -49,6 +49,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply SPI_FLASH_ISSI
 	imply SYSRESET
 	imply SYSRESET_GPIO
+	imply SPL_SYSRESET_GPIO if SPL
 	imply CMD_I2C
 
 endif

board/sifive/unmatched/Kconfig

@@ -48,6 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply PHY_MSCC
 	imply SYSRESET
 	imply SYSRESET_GPIO
+	imply SPL_SYSRESET_GPIO if SPL
 	imply CMD_I2C
 
 endif

board/toradex/apalis_t30/Kconfig

@@ -7,7 +7,7 @@ config SYS_VENDOR
 	default "toradex"
 
 config SYS_CONFIG_NAME
-	default "apalis_t30"
+	default "tegra"
 
 config TDX_CFG_BLOCK
 	default y

board/toradex/apalis_t30/apalis_t30.env

@@ -1,6 +1,15 @@
 uboot_hwpart=1
 uboot_blk=0
 
+/*
+ * Board-specific serial config
+ *
+ * Apalis UART1: NVIDIA UARTA
+ * Apalis UART2: NVIDIA UARTD
+ * Apalis UART3: NVIDIA UARTB
+ * Apalis UART4: NVIDIA UARTC
+ */
+
 set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff &&
 	setexpr blkcnt ${blkcnt} / 0x200
 update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} &&

board/toradex/colibri_t20/Kconfig

@@ -7,7 +7,7 @@ config SYS_VENDOR
 	default "toradex"
 
 config SYS_CONFIG_NAME
-	default "colibri_t20"
+	default "tegra"
 
 config TDX_CFG_BLOCK
 	default y

board/toradex/colibri_t20/colibri_t20.c

@@ -147,7 +147,7 @@ void pin_mux_usb(void)
 }
 #endif
 
-#ifdef CONFIG_VIDEO_TEGRA20
+#ifdef CONFIG_VIDEO_TEGRA
 /*
  * Routine: pin_mux_display
  * Description: setup the pin muxes/tristate values for the LCD interface)

board/toradex/colibri_t30/Kconfig

@@ -7,7 +7,7 @@ config SYS_VENDOR
 	default "toradex"
 
 config SYS_CONFIG_NAME
-	default "colibri_t30"
+	default "tegra"
 
 config TDX_CFG_BLOCK
 	default y

board/toradex/colibri_t30/colibri_t30.env

@@ -1,6 +1,14 @@
 uboot_hwpart=1
 uboot_blk=0
 
+/*
+ * Board-specific serial config
+ *
+ * Colibri UART-A: NVIDIA UARTA
+ * Colibri UART-B: NVIDIA UARTD
+ * Colibri UART-C: NVIDIA UARTB
+ */
+
 set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff &&
 	setexpr blkcnt ${blkcnt} / 0x200
 update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} &&

board/wexler/qc750/Kconfig

@@ -7,6 +7,10 @@ config SYS_VENDOR
 	default "wexler"
 
 config SYS_CONFIG_NAME
-	default "qc750"
+	default "tegra"
+
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Wexler QC750"
 
 endif

board/xiaomi/mocha/Kconfig

@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "mocha"
 
+config TEGRA_BOARD_STRING
+	string "Default Tegra board name"
+	default "Xiaomi Mocha"
+
 endif

configs/endeavoru_defconfig

@@ -83,5 +83,5 @@ CONFIG_VIDEO=y
 CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_VIDEO_LCD_ENDEAVORU=y
-CONFIG_VIDEO_DSI_TEGRA30=y
+CONFIG_VIDEO_DSI_TEGRA=y
 CONFIG_TEGRA_BACKLIGHT_PWM=y

configs/ge_b1x5v2_defconfig

@@ -116,6 +116,7 @@ CONFIG_MXC_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_CMD_POWEROFF=y
 CONFIG_POWEROFF_GPIO=y
+CONFIG_SPL_POWEROFF_GPIO=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y

configs/grouper_defconfig

@@ -88,4 +88,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4e41
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_LOGO is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

configs/harmony_defconfig

@@ -64,5 +64,5 @@ CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
 CONFIG_CONSOLE_SCROLL_LINES=10

configs/ideapad-yoga-11_defconfig

@@ -83,4 +83,4 @@ CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_VIDEO_BRIDGE_PARADE_DP501=y
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

configs/medcom-wide_defconfig

@@ -53,4 +53,4 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

configs/microblaze-generic_defconfig

@@ -97,6 +97,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_XILINX_UARTLITE=y
 CONFIG_XILINX_SPI=y
 CONFIG_SYSRESET_GPIO=y
+CONFIG_SPL_SYSRESET_GPIO=y
 CONFIG_SYSRESET_MICROBLAZE=y
 CONFIG_WDT=y
 CONFIG_XILINX_TB_WATCHDOG=y

configs/mocha_defconfig

@@ -89,4 +89,4 @@ CONFIG_VIDEO_FONT_16X32=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_VIDEO_LCD_SHARP_LQ079L1SX01=y
 CONFIG_BACKLIGHT_LP855x=y
-CONFIG_VIDEO_DSI_TEGRA30=y
+CONFIG_VIDEO_DSI_TEGRA=y

configs/mot_defconfig

@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x00110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="mot"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus"
+CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_TEGRA20=y
+CONFIG_TARGET_MOT=y
+CONFIG_TEGRA_ENABLE_UARTB=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_SYS_PBSIZE=2085
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra20 (Mot) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x11000000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_CPCAP_POWER_BUTTON=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_CPCAP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_CPCAP=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_POWEROFF_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Motorola"
+CONFIG_USB_GADGET_VENDOR_NUM=0x22b8
+CONFIG_USB_GADGET_PRODUCT_NUM=0x708c
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_MOT=y
+CONFIG_BACKLIGHT_LM3532=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_DSI_TEGRA=y

configs/paz00_defconfig

@@ -53,5 +53,5 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
 CONFIG_I2C_EDID=y
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
 CONFIG_CONSOLE_SCROLL_LINES=10

configs/picasso_defconfig

@@ -81,4 +81,4 @@ CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_LOGO is not set
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

configs/qc750_defconfig

@@ -80,4 +80,4 @@ CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_LOGO is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

configs/seaboard_defconfig

@@ -60,5 +60,5 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
 CONFIG_CONSOLE_SCROLL_LINES=10

configs/surface-rt_defconfig

@@ -79,4 +79,4 @@ CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_LOGO is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

configs/tec_defconfig

@@ -53,4 +53,4 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

configs/tegratab_defconfig

@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="tegratab"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra114-nvidia-tegratab"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA114=y
+CONFIG_TARGET_TEGRATAB=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_SYS_PBSIZE=2086
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra114 (TegraTab) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_TEGRA_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_PALMAS_GPIO=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_PALMAS=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_LG_LD070WX3=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_DSI_TEGRA=y

configs/tf701t_defconfig

@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="transformer-t114"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra114-asus-tf701t"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA114=y
+CONFIG_TARGET_TRANSFORMER_T114=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_SYS_PBSIZE=2086
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra114 (Transformer) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_TEGRA_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_PALMAS_GPIO=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_PALMAS=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="ASUS"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_FONT_8X16 is not set
+CONFIG_VIDEO_FONT_16X32=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_DSI_TEGRA=y

configs/transformer_t20_defconfig

@@ -81,4 +81,4 @@ CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_LOGO is not set
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

configs/transformer_t30_defconfig

@@ -93,5 +93,5 @@ CONFIG_VIDEO=y
 CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
 CONFIG_VIDEO_HDMI_TEGRA=y

configs/ventana_defconfig

@@ -53,5 +53,5 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y
 CONFIG_CONSOLE_SCROLL_LINES=10

configs/x3_t30_defconfig

@@ -87,4 +87,4 @@ CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_BACKLIGHT_LM3533=y
 CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y
-CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_TEGRA=y

doc/board/asus/index.rst

@@ -9,3 +9,4 @@ ASUS
    grouper
    transformer_t20
    transformer_t30
+   transformer_t114

doc/board/asus/transformer_t114.rst

@@ -0,0 +1,74 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the ASUS Transformer device family
+=============================================
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot U-Boot by loading it into RAM (coldboot)
+- Chainloading U-Boot from the vendor bootloader
+- Boot
+
+Build U-Boot
+------------
+
+U-Boot can be built in two forms: U-Boot with SPL, which is used for booting
+by loading directly into RAM and U-Boot without SPL, which can be flashed
+and chainloaded from the vendor bootloader.
+
+To build U-Boot with SPL proseed:
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=arm-none-eabi-
+    $ make tf701t_defconfig
+    $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+file, ready for cold booting by loading into RAM.
+
+To build U-Boot without SPL adjust tf701t_defconfig:
+
+.. code-block::
+
+  CONFIG_TEXT_BASE=0x80A00000
+  CONFIG_SKIP_LOWLEVEL_INIT=y
+  # CONFIG_OF_BOARD_SETUP is not set
+  CONFIG_TEGRA_SUPPORT_NON_SECURE=y
+
+After the build succeeds, you will obtain the final ``u-boot-dtb.bin`` file,
+ready for booting with fastboot boot or which can be further processed into
+a flashable boot.img.
+
+Boot U-Boot by loading it into RAM (coldboot)
+---------------------------------------------
+
+Done fairly simply by using fusee-tools (using run_bootloader.sh) and placing
+``u-boot-dtb-tegra.bin`` generated on the previous step into fusee-tools dir.
+This method requires constant access to the host PC or payloader and can fully
+eliminate influence of the vendor bootloader onto the boot process.
+
+.. code-block:: bash
+
+    $ ./run_bootloader.sh -s T114 -t ./bct/tf701t.bct
+
+Chainloading U-Boot from the vendor bootloader
+----------------------------------------------
+
+``u-boot-dtb.bin`` has to be further packed into Android boot image form,
+where ``u-boot-dtb.bin`` acts as kernel, while dtb and ramdisk parts should
+not be included. Then the generated boot image can be flashed into the /boot
+partition of the tablet using vendor bootloader's fastboot and will act as
+the bootloader of the last stage.
+
+Boot
+----
+In both cases after U-Boot obtains control it performs search of extlinux.conf
+first on the dock USB device is available, then on MicroSD card if available
+and lastly on eMMC. If none of the devices above are present, then the device
+is turned off.
+
+If during boot of U-Boot Volume Down button is pressed, the device will enter
+U-Boot bootmenu.

doc/board/index.rst

@@ -41,6 +41,8 @@ Board-specific doc
    mediatek/index
    microchip/index
    microsoft/index
+   motorola/index
+   nvidia/index
    nxp/index
    openpiton/index
    ouya/index

doc/board/motorola/index.rst

@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Motorola
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   mot

doc/board/motorola/mot.rst

@@ -0,0 +1,104 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Motorola Atrix 4G (MB860) and Droid X2 (MB870)
+=============================================================
+
+``DISCLAMER!`` Moving your device to use U-Boot assumes replacement of the
+vendor bootloader. Vendor Android firmwares will no longer be able to run on
+the device. This replacement IS reversible if you have backups.
+
+Quick Start
+-----------
+
+- Prerequisites
+- Build U-Boot
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Boot
+- Self Upgrading
+
+Prerequisites
+-------------
+
+In order to work with RCM/APX mode, both devices require a factory cable which
+is made by routing 5V to the ID pin of a micro-USB cable (5v is applied to both
+ID and dedicated 5v). This way, the host PC can detect the device in RCM mode,
+and the device can operate without a battery.
+
+Build U-Boot
+------------
+
+Device support is implemented by applying config fragment to a generic
+board defconfig. Valid fragments are ``daytona.config`` and ``olympus.config``.
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=arm-none-eabi-
+    $ make mot_defconfig olympus.config # For Atrix 4G
+    $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for further processing.
+
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or to
+recover the device in case of a failed update. You need to know your device
+individual SBK to continue.
+
+.. code-block:: bash
+
+    $ git clone https://gitlab.com/grate-driver/re-crypt.git
+    $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+    $ ./re-crypt.py --dev olympus --sbk <your sbk> --split
+
+where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX``
+
+The script will produce ``bct.img`` and ``ebt.img`` ready to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+    $ fastboot flash 0.1 bct.img
+    $ fastboot flash 0.2 ebt.img
+    $ fastboot reboot
+
+Device will reboot.
+
+Boot
+----
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while booting, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console
+and update bootloader (check the next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card
+and insert it into the device. Enter bootmenu, choose update the bootloader
+option with the Power button and U-Boot should update itself. Once the process
+is completed, U-Boot will ask to press any button to reboot.