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drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration

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FPGA configuration encounters failure when the cache is not flushed.
Add cache flushing to the memory region that holds the FPGA
configuration bitstream.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Link: https://lore.kernel.org/r/20250506012851.30039-1-nareshkumar.ravulapalli@altera.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Naresh Kumar Ravulapalli
2025-05-05 18:28:51 -07:00
committed by Michal Simek
parent 967eebcd85
commit 85f181b194
1 changed files with 7 additions and 0 deletions
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7
drivers/fpga/intel_sdm_mb.c
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@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Intel Corporation <www.intel.com>
* Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include <altera.h>
@@ -9,6 +10,8 @@
#include <watchdog.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/smc_api.h>
#include <asm/cache.h>
#include <cpu_func.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/intel-smc.h>
@@ -738,6 +741,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
debug("Invoking FPGA_CONFIG_START...\n");
flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
if (ret) {
@@ -1023,6 +1028,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
u32 resp_len = 2;
u32 resp_buf[2];
flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
debug("Sending MBOX_RECONFIG...\n");
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
NULL, 0, &resp_len, resp_buf);