Merge tag 'xilinx-for-v2025.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx/FPGA changes for v2025.07-rc4

usb:
- Fix regulator handling

net:
- Fix MII clock handling

phy:
- Fix GTR line logic for sgmii

pci:
- Fix pcireg_base logic

fpga:
- Fix change handling in intel_sdm_mb driver

common/usb_onboard_hub.c

@@ -146,7 +146,7 @@ static int usb_onboard_hub_probe(struct udevice *dev)
 	int ret;
 
 	ret = device_get_supply_regulator(dev, "vdd-supply", &hub->vdd);
-	if (ret && ret != -ENOENT) {
+	if (ret && ret != -ENOENT && ret != -ENOSYS) {
 		dev_err(dev, "can't get vdd-supply: %d\n", ret);
 		return ret;
 	}
@@ -204,14 +204,16 @@ static int usb_onboard_hub_bind(struct udevice *dev)
 static int usb_onboard_hub_remove(struct udevice *dev)
 {
 	struct onboard_hub *hub = dev_get_priv(dev);
-	int ret;
+	int ret = 0;
 
 	if (hub->reset_gpio)
 		dm_gpio_free(hub->reset_gpio->dev, hub->reset_gpio);
 
-	ret = regulator_set_enable_if_allowed(hub->vdd, false);
-	if (ret)
-		dev_err(dev, "can't disable vdd-supply: %d\n", ret);
+	if (hub->vdd) {
+		ret = regulator_set_enable_if_allowed(hub->vdd, false);
+		if (ret)
+			dev_err(dev, "can't disable vdd-supply: %d\n", ret);
+	}
 
 	return ret;
 }

drivers/fpga/intel_sdm_mb.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #include <altera.h>
@@ -9,6 +10,8 @@
 #include <watchdog.h>
 #include <asm/arch/mailbox_s10.h>
 #include <asm/arch/smc_api.h>
+#include <asm/cache.h>
+#include <cpu_func.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/intel-smc.h>
@@ -738,6 +741,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	debug("Invoking FPGA_CONFIG_START...\n");
 
+	flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
+
 	ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
 
 	if (ret) {
@@ -1023,6 +1028,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	u32 resp_len = 2;
 	u32 resp_buf[2];
 
+	flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
+
 	debug("Sending MBOX_RECONFIG...\n");
 	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
 			    NULL, 0, &resp_len, resp_buf);

drivers/net/zynq_gem.c

@@ -567,12 +567,14 @@ static int zynq_gem_init(struct udevice *dev)
 	}
 #endif
 
-	ret = clk_get_rate(&priv->tx_clk);
-	if (ret != clk_rate) {
-		ret = clk_set_rate(&priv->tx_clk, clk_rate);
-		if (IS_ERR_VALUE(ret)) {
-			dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate);
-			return ret;
+	if (priv->interface != PHY_INTERFACE_MODE_MII) {
+		ret = clk_get_rate(&priv->tx_clk);
+		if (ret != clk_rate) {
+			ret = clk_set_rate(&priv->tx_clk, clk_rate);
+			if (IS_ERR_VALUE(ret)) {
+				dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate);
+				return ret;
+			}
 		}
 	}
 

drivers/pci/pcie-xilinx-nwl.c

@@ -303,6 +303,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie)
 		return PTR_ERR(pcie->breg_base);
 	pcie->phys_breg_base = res.start;
 
+	ret = dev_read_resource_byname(dev, "pcireg", &res);
+	if (ret)
+		return ret;
+	pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res));
+	if (IS_ERR(pcie->pcireg_base))
+		return PTR_ERR(pcie->pcireg_base);
+
 	ret = dev_read_resource_byname(dev, "cfg", &res);
 	if (ret)
 		return ret;

drivers/phy/phy-zynqmp.c

@@ -138,6 +138,7 @@
 #define PROT_BUS_WIDTH_40		0x2
 #define PROT_BUS_WIDTH_MASK		0x3
 #define PROT_BUS_WIDTH_SHIFT		2
+#define GEM_CLK_CTRL_WIDTH_SHIFT	5
 
 /* Number of GT lanes */
 #define NUM_LANES			4
@@ -400,6 +401,7 @@ static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
 {
 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
 	u32 shift = gtr_phy->lane * PROT_BUS_WIDTH_SHIFT;
+	u32 clk_ctrl_shift = gtr_phy->lane * GEM_CLK_CTRL_WIDTH_SHIFT;
 
 	/* Set SGMII protocol TX and RX bus width to 10 bits. */
 	xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, PROT_BUS_WIDTH_MASK << shift,
@@ -417,9 +419,9 @@ static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
 	 */
 	/* GEM I/O Clock Control */
 	clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CLK_CTRL,
-			0xf << shift,
+			0xf << clk_ctrl_shift,
 			(GEM_CTRL_GEM_SGMII_MODE | GEM_CTRL_GEM_REF_SRC_SEL) <<
-			shift);
+			clk_ctrl_shift);
 
 	/* Setup signal detect */
 	clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CTRL,