Merge tag 'u-boot-rockchip-next-20240615' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/21113 - New board: Theobroma Systems SOM-RK3588-Q7 Tiger, ArmSoM Sige7 Rk3588; - PX30 dts migrate to OF_UPSTREAM; - Some other update on board or config;
This commit is contained in:
Tom Rini
@@ -534,6 +534,7 @@ F: arch/arm/include/asm/arch-rockchip/
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F: arch/arm/mach-rockchip/
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F: board/amarula/vyasa-rk3288/
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F: board/anbernic/rgxx3_rk3566/
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F: board/armsom/sige7-rk3588/
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F: board/chipspark/popmetal_rk3288
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F: board/engicam/px30_core/
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F: board/firefly/
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@@ -52,14 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \
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dtb-$(CONFIG_MACH_S700) += \
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s700-cubieboard7.dtb
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dtb-$(CONFIG_ROCKCHIP_PX30) += \
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px30-evb.dtb \
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px30-firefly.dtb \
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px30-engicam-px30-core-ctouch2.dtb \
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px30-engicam-px30-core-ctouch2-of10.dtb \
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px30-engicam-px30-core-edimm2.2.dtb \
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rk3326-odroid-go2.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3036) += \
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rk3036-sdk.dtb
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@@ -1,129 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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/ {
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aliases {
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mmc1 = &sdmmc;
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mmc2 = &sdio;
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};
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vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys"; /* +5V */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&xin32k>;
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clock-names = "ext_clock";
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post-power-on-delay-ms = <80>;
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_enable_h>;
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};
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vcc3v3_btreg: vcc3v3-btreg {
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compatible = "regulator-gpio";
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enable-active-high;
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pinctrl-names = "default";
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pinctrl-0 = <&bt_enable_h>;
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regulator-name = "btreg-gpio-supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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states = <3300000 0x0>;
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};
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vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_rf_aux_mod";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc5v0_sys>;
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};
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xin32k: xin32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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};
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};
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&sdio {
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#address-cells = <1>;
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#size-cells = <0>;
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bus-width = <4>;
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clock-frequency = <50000000>;
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cap-sdio-irq;
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cap-sd-highspeed;
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keep-power-in-suspend;
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mmc-pwrseq = <&sdio_pwrseq>;
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non-removable;
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sd-uhs-sdr104;
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status = "okay";
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brcmf: wifi@1 {
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compatible = "brcm,bcm4329-fmac";
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reg = <1>;
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};
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};
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&gmac {
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clock_in_out = "output";
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phy-supply = <&vcc_3v3>; /* +3V3_SOM */
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snps,reset-active-low;
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snps,reset-delays-us = <0 50000 50000>;
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snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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};
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&sdmmc {
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cap-sd-highspeed;
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card-detect-delay = <800>;
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vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */
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vqmmc-supply = <&vcc_3v3>;
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status = "okay";
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};
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&u2phy {
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status = "okay";
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u2phy_host: host-port {
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status = "okay";
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};
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u2phy_otg: otg-port {
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status = "okay";
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};
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};
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&uart2 {
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pinctrl-0 = <&uart2m1_xfer>;
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status = "okay";
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};
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&usb20_otg {
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status = "okay";
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};
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&usb_host0_ehci {
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status = "okay";
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};
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&usb_host0_ohci {
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status = "okay";
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};
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@@ -1,30 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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#include "px30-engicam-common.dtsi"
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&pinctrl {
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bt {
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bt_enable_h: bt-enable-h {
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rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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sdio-pwrseq {
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wifi_enable_h: wifi-enable-h {
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rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&sdio_pwrseq {
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reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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};
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&vcc3v3_btreg {
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enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
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};
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@@ -1,66 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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#include "px30-engicam-common.dtsi"
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/ {
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm0 0 25000 0>;
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};
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panel {
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compatible = "yes-optoelectronics,ytc700tlag-05-201c";
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backlight = <&backlight>;
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data-mapping = "vesa-24";
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power-supply = <&vcc3v3_lcd>;
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port {
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panel_in_lvds: endpoint {
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remote-endpoint = <&lvds_out_panel>;
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};
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};
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};
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};
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&display_subsystem {
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status = "okay";
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};
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&dsi_dphy {
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status = "okay";
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};
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/* LVDS_B(secondary) */
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&lvds {
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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lvds_out_panel: endpoint {
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remote-endpoint = <&panel_in_lvds>;
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};
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};
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};
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};
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&vopb {
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status = "okay";
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};
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&vopb_mmu {
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status = "okay";
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};
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&vopl {
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status = "okay";
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};
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&vopl_mmu {
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status = "okay";
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};
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@@ -1,77 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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/dts-v1/;
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#include "px30.dtsi"
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#include "px30-engicam-ctouch2.dtsi"
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#include "px30-engicam-px30-core.dtsi"
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/ {
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model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
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compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
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"rockchip,px30";
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm0 0 25000 0>;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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};
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panel {
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compatible = "ampire,am-1280800n3tzqw-t00h";
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backlight = <&backlight>;
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power-supply = <&vcc3v3_lcd>;
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data-mapping = "vesa-24";
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port {
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panel_in_lvds: endpoint {
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remote-endpoint = <&lvds_out_panel>;
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};
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};
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};
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};
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&display_subsystem {
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status = "okay";
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};
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&dsi_dphy {
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status = "okay";
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};
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&lvds {
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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lvds_out_panel: endpoint {
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remote-endpoint = <&panel_in_lvds>;
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};
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};
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};
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};
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&vopb {
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status = "okay";
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};
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&vopb_mmu {
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status = "okay";
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};
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&vopl {
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status = "okay";
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};
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&vopl_mmu {
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status = "okay";
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};
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@@ -1,22 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions
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* Copyright (c) 2020 Amarula Solutions(India)
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||||
*/
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/dts-v1/;
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#include "px30.dtsi"
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#include "px30-engicam-ctouch2.dtsi"
|
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#include "px30-engicam-px30-core.dtsi"
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/ {
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model = "Engicam PX30.Core C.TOUCH 2.0";
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compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
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"rockchip,px30";
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chosen {
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stdout-path = "serial2:115200n8";
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};
|
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};
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@@ -1,43 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
||||
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||||
/dts-v1/;
|
||||
#include "px30.dtsi"
|
||||
#include "px30-engicam-edimm2.2.dtsi"
|
||||
#include "px30-engicam-px30-core.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
|
||||
compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
|
||||
"rockchip,px30";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bt {
|
||||
bt_enable_h: bt-enable-h {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdio_pwrseq {
|
||||
reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&vcc3v3_btreg {
|
||||
enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
@@ -1,241 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutons
|
||||
* Copyright (c) 2020 Amarula Solutons(India)
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
/ {
|
||||
compatible = "engicam,px30-core", "rockchip,px30";
|
||||
|
||||
aliases {
|
||||
mmc0 = &emmc;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_log: DCDC_REG1 {
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_arm: DCDC_REG2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: DCDC_REG4 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sys: DCDC_REG5 {
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v0: LDO_REG1 {
|
||||
regulator-name = "vcc_1v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: LDO_REG2 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v0: LDO_REG3 {
|
||||
regulator-name = "vdd_1v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_pmu: LDO_REG4 {
|
||||
regulator-name = "vcc3v0_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_lcd: SWITCH_REG1 {
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_lcd";
|
||||
};
|
||||
|
||||
vcc5v0_host: SWITCH_REG2 {
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
vccio1-supply = <&vcc_3v3>;
|
||||
vccio2-supply = <&vcc_3v3>;
|
||||
vccio3-supply = <&vcc_3v3>;
|
||||
vccio4-supply = <&vcc_3v3>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc_3v3>;
|
||||
pmuio2-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,634 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "px30.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip PX30 EVB";
|
||||
compatible = "rockchip,px30-evb", "rockchip,px30";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc;
|
||||
mmc1 = &sdio;
|
||||
mmc2 = &emmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial5:115200n8";
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 2>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
poll-interval = <100>;
|
||||
|
||||
esc-key {
|
||||
label = "esc";
|
||||
linux,code = <KEY_ESC>;
|
||||
press-threshold-microvolt = <1310000>;
|
||||
};
|
||||
|
||||
home-key {
|
||||
label = "home";
|
||||
linux,code = <KEY_HOME>;
|
||||
press-threshold-microvolt = <624000>;
|
||||
};
|
||||
|
||||
menu-key {
|
||||
label = "menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
press-threshold-microvolt = <987000>;
|
||||
};
|
||||
|
||||
vol-down-key {
|
||||
label = "volume down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
press-threshold-microvolt = <300000>;
|
||||
};
|
||||
|
||||
vol-up-key {
|
||||
label = "volume up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
press-threshold-microvolt = <17000>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 25000 0>;
|
||||
power-supply = <&vcc3v3_lcd>;
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
pinctrl-0 = <&emmc_reset>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
|
||||
};
|
||||
|
||||
vcc5v0_sys: vccsys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&csi_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
mipi_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mipi_out_panel: endpoint {
|
||||
remote-endpoint = <&mipi_in_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel@0 {
|
||||
compatible = "xinpeng,xpp055c272";
|
||||
reg = <0>;
|
||||
backlight = <&backlight>;
|
||||
iovcc-supply = <&vcc_1v8>;
|
||||
vci-supply = <&vcc3v3_lcd>;
|
||||
|
||||
port {
|
||||
mipi_in_panel: endpoint {
|
||||
remote-endpoint = <&mipi_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emmc {
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
vmmc-supply = <&vcc_3v0>;
|
||||
vqmmc-supply = <&vccio_flash>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
clock_in_out = "output";
|
||||
phy-supply = <&vcc_rmii>;
|
||||
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 50000 50000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_log>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "xin32k";
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_log: DCDC_REG1 {
|
||||
regulator-name = "vdd_log";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_arm: DCDC_REG2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: vcc_rmii: DCDC_REG4 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sys: DCDC_REG5 {
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v0: LDO_REG1 {
|
||||
regulator-name = "vcc_1v0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v0: LDO_REG3 {
|
||||
regulator-name = "vdd_1v0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_pmu: LDO_REG4 {
|
||||
regulator-name = "vcc3v0_pmu";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd: LDO_REG6 {
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc2v8_dvp: LDO_REG7 {
|
||||
regulator-name = "vcc2v8_dvp";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <2800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_dvp: LDO_REG8 {
|
||||
regulator-name = "vcc1v8_dvp";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v5_dvp: LDO_REG9 {
|
||||
regulator-name = "vcc1v5_dvp";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_lcd: SWITCH_REG1 {
|
||||
regulator-name = "vcc3v3_lcd";
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc5v0_host: SWITCH_REG2 {
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
sensor@d {
|
||||
compatible = "asahi-kasei,ak8963";
|
||||
reg = <0x0d>;
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
vdd-supply = <&vcc3v0_pmu>;
|
||||
mount-matrix = "1", /* x0 */
|
||||
"0", /* y0 */
|
||||
"0", /* z0 */
|
||||
"0", /* x1 */
|
||||
"1", /* y1 */
|
||||
"0", /* z1 */
|
||||
"0", /* x2 */
|
||||
"0", /* y2 */
|
||||
"1"; /* z2 */
|
||||
};
|
||||
|
||||
touchscreen@14 {
|
||||
compatible = "goodix,gt1151";
|
||||
reg = <0x14>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
|
||||
irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
VDDIO-supply = <&vcc3v3_lcd>;
|
||||
};
|
||||
|
||||
sensor@4c {
|
||||
compatible = "fsl,mma7660";
|
||||
reg = <0x4c>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* These are relatively safe rise/fall times; TODO: measure */
|
||||
i2c-scl-falling-time-ns = <50>;
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
|
||||
ov5695: ov5695@36 {
|
||||
compatible = "ovti,ov5695";
|
||||
reg = <0x36>;
|
||||
avdd-supply = <&vcc2v8_dvp>;
|
||||
clocks = <&cru SCLK_CIF_OUT>;
|
||||
clock-names = "xvclk";
|
||||
dvdd-supply = <&vcc1v5_dvp>;
|
||||
dovdd-supply = <&vcc1v8_dvp>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cif_clkout_m0>;
|
||||
reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
port {
|
||||
ucam_out: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s1_2ch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
vccio1-supply = <&vccio_sdio>;
|
||||
vccio2-supply = <&vccio_sd>;
|
||||
vccio3-supply = <&vcc_3v0>;
|
||||
vccio4-supply = <&vcc3v0_pmu>;
|
||||
vccio5-supply = <&vcc_3v0>;
|
||||
vccio6-supply = <&vccio_flash>;
|
||||
};
|
||||
|
||||
&isp {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
mipi_in_ucam: endpoint@0 {
|
||||
reg = <0>;
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&ucam_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&isp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
headphone {
|
||||
hp_det: hp-det {
|
||||
rockchip,pins =
|
||||
<2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_reset: emmc-reset {
|
||||
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins =
|
||||
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
soc_slppin_gpio: soc_slppin_gpio {
|
||||
rockchip,pins =
|
||||
<0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
soc_slppin_slp: soc_slppin_slp {
|
||||
rockchip,pins =
|
||||
<0 RK_PA4 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
soc_slppin_rst: soc_slppin_rst {
|
||||
rockchip,pins =
|
||||
<0 RK_PA4 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins =
|
||||
<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
status = "okay";
|
||||
|
||||
pmuio1-supply = <&vcc3v0_pmu>;
|
||||
pmuio2-supply = <&vcc3v0_pmu>;
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <800>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio {
|
||||
cap-sd-highspeed;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy {
|
||||
status = "okay";
|
||||
|
||||
u2phy_host: host-port {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
u2phy_otg: otg-port {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer &uart1_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb20_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -15,14 +15,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&binman {
|
||||
simple-bin {
|
||||
fit {
|
||||
offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&emmc_clk {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@@ -1,232 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "px30-ringneck.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit";
|
||||
compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
|
||||
|
||||
aliases {
|
||||
mmc2 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&haikou_keys_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button-batlow-n {
|
||||
label = "BATLOW#";
|
||||
linux,code = <KEY_BATTERY>;
|
||||
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button-slp-btn-n {
|
||||
label = "SLP_BTN#";
|
||||
linux,code = <KEY_SLEEP>;
|
||||
gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button-wake-n {
|
||||
label = "WAKE#";
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
switch-lid-btn-n {
|
||||
label = "LID_BTN#";
|
||||
linux,code = <SW_LID>;
|
||||
linux,input-type = <EV_SW>;
|
||||
gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
|
||||
|
||||
sd_card_led: led-1 {
|
||||
gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc2";
|
||||
function = LED_FUNCTION_SD;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s0-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Haikou,I2S-codec";
|
||||
simple-audio-card,mclk-fs = <512>;
|
||||
|
||||
simple-audio-card,codec {
|
||||
clocks = <&sgtl5000_clk>;
|
||||
sound-dai = <&sgtl5000>;
|
||||
};
|
||||
|
||||
simple-audio-card,cpu {
|
||||
bitclock-master;
|
||||
frame-master;
|
||||
sound-dai = <&i2s0_8ch>;
|
||||
};
|
||||
};
|
||||
|
||||
sgtl5000_clk: sgtl5000-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
dc_12v: dc-12v-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc3v3_baseboard: vcc3v3-baseboard-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_baseboard";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_baseboard: vcc5v0-baseboard-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_baseboard";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vdda_codec: vdda-codec-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdda_codec";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_baseboard>;
|
||||
};
|
||||
|
||||
vddd_codec: vddd-codec-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddd_codec";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <1600000>;
|
||||
vin-supply = <&vcc5v0_baseboard>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
sgtl5000: codec@a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&sgtl5000_clk>;
|
||||
#sound-dai-cells = <0>;
|
||||
VDDA-supply = <&vdda_codec>;
|
||||
VDDIO-supply = <&vcc3v3_baseboard>;
|
||||
VDDD-supply = <&vddd_codec>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
eeprom@50 {
|
||||
reg = <0x50>;
|
||||
compatible = "atmel,24c01";
|
||||
pagesize = <8>;
|
||||
size = <128>;
|
||||
vcc-supply = <&vcc3v3_baseboard>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
haikou {
|
||||
haikou_keys_pin: haikou-keys-pin {
|
||||
rockchip,pins =
|
||||
/* WAKE# */
|
||||
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
/* SLP_BTN# */
|
||||
<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
/* LID_BTN */
|
||||
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
/* BATLOW# */
|
||||
<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
/* BIOS_DISABLE# */
|
||||
<2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
sd_card_led_pin: sd-card-led-pin {
|
||||
rockchip,pins =
|
||||
<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
vmmc-supply = <&vcc3v3_baseboard>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-0 = <&uart5_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb20_otg {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,382 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "px30.dtsi"
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc0 = &emmc;
|
||||
mmc1 = &sdio;
|
||||
rtc0 = &rtc_twi;
|
||||
rtc1 = &rk809;
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
pinctrl-0 = <&emmc_reset>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&module_led_pin>;
|
||||
status = "okay";
|
||||
|
||||
module_led: led-0 {
|
||||
gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
linux,default-trigger = "heartbeat";
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0_sys: vccsys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
supports-emmc;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
non-removable;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_emmc>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* On-module TI DP83825I PHY but no connector, enable in carrierboard */
|
||||
&gmac {
|
||||
snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 50000 50000>;
|
||||
phy-supply = <&vcc_3v3>;
|
||||
clock_in_out = "output";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
/*
|
||||
* The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module
|
||||
* eMMC powered-down initially (in fact it keeps the reset signal
|
||||
* asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after
|
||||
* the SPL has been booted from SD Card.
|
||||
*/
|
||||
bios-disable-override-hog {
|
||||
gpios = <RK_PB5 GPIO_ACTIVE_LOW>;
|
||||
output-high;
|
||||
line-name = "bios_disable_override";
|
||||
gpio-hog;
|
||||
};
|
||||
|
||||
/*
|
||||
* The BIOS_DISABLE hog is a feedback pin for the actual status of the
|
||||
* signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually
|
||||
* represents the state of a switch on the baseboard.
|
||||
*/
|
||||
bios-disable-n-hog {
|
||||
gpios = <RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
line-name = "bios_disable";
|
||||
input;
|
||||
gpio-hog;
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
pinctrl-names = "default";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "xin32k";
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc_3v3>;
|
||||
vcc6-supply = <&vcc_3v3>;
|
||||
vcc7-supply = <&vcc_3v3>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_log: DCDC_REG1 {
|
||||
regulator-name = "vdd_log";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_arm: DCDC_REG2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0_1v8: vcc_emmc: DCDC_REG4 {
|
||||
regulator-name = "vcc_3v0_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: DCDC_REG5 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: LDO_REG2 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v0: LDO_REG3 {
|
||||
regulator-name = "vcc_1v0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_lcd: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vcc_lcd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_lcd: LDO_REG8 {
|
||||
regulator-name = "vcc_1v8_lcd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG9 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
/* SE05x is limited to Fast Mode */
|
||||
clock-frequency = <400000>;
|
||||
|
||||
fan: fan@18 {
|
||||
compatible = "ti,amc6821";
|
||||
reg = <0x18>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
rtc_twi: rtc@6f {
|
||||
compatible = "isil,isl1208";
|
||||
reg = <0x6f>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s0_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
|
||||
pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx
|
||||
&i2s0_8ch_sdo0 &i2s0_8ch_sdi0>;
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
vccio1-supply = <&vcc_3v3>;
|
||||
vccio2-supply = <&vccio_sd>;
|
||||
vccio3-supply = <&vcc_3v3>;
|
||||
vccio4-supply = <&vcc_3v3>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_emmc>;
|
||||
vccio-oscgpi-supply = <&vcc_3v3>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
emmc {
|
||||
emmc_reset: emmc-reset {
|
||||
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
module_led_pin: module-led-pin {
|
||||
rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins =
|
||||
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Mule UCAN */
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -33,11 +33,27 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart2m0_xfer {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
clock-frequency = <24000000>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart5_cts {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart5_rts {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart5_xfer {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bootph-all;
|
||||
|
||||
|
||||
@@ -74,6 +74,21 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&rk817 {
|
||||
regulators {
|
||||
vcc_cam: LDO_REG9 {
|
||||
regulator-name = "vcc_cam";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
|
||||
@@ -1,642 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Hardkernel Co., Ltd
|
||||
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3326.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ODROID-GO Advance";
|
||||
compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
adc-joystick {
|
||||
compatible = "adc-joystick";
|
||||
io-channels = <&saradc 1>,
|
||||
<&saradc 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
axis@0 {
|
||||
reg = <0>;
|
||||
abs-flat = <10>;
|
||||
abs-fuzz = <10>;
|
||||
abs-range = <172 772>;
|
||||
linux,code = <ABS_X>;
|
||||
};
|
||||
|
||||
axis@1 {
|
||||
reg = <1>;
|
||||
abs-flat = <10>;
|
||||
abs-fuzz = <10>;
|
||||
abs-range = <278 815>;
|
||||
linux,code = <ABS_Y>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
power-supply = <&vcc_bl>;
|
||||
pwms = <&pwm1 0 25000 0>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&btn_pins>;
|
||||
|
||||
/*
|
||||
* *** ODROIDGO2-Advance Switch layout ***
|
||||
* |------------------------------------------------|
|
||||
* | sw15 sw16 |
|
||||
* |------------------------------------------------|
|
||||
* | sw1 |-------------------| sw8 |
|
||||
* | sw3 sw4 | | sw7 sw5 |
|
||||
* | sw2 | LCD Display | sw6 |
|
||||
* | | | |
|
||||
* | |-------------------| |
|
||||
* | sw9 sw10 sw11 sw12 sw13 sw14 |
|
||||
* |------------------------------------------------|
|
||||
*/
|
||||
|
||||
sw1 {
|
||||
gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
|
||||
label = "DPAD-UP";
|
||||
linux,code = <BTN_DPAD_UP>;
|
||||
};
|
||||
sw2 {
|
||||
gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
|
||||
label = "DPAD-DOWN";
|
||||
linux,code = <BTN_DPAD_DOWN>;
|
||||
};
|
||||
sw3 {
|
||||
gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
label = "DPAD-LEFT";
|
||||
linux,code = <BTN_DPAD_LEFT>;
|
||||
};
|
||||
sw4 {
|
||||
gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
label = "DPAD-RIGHT";
|
||||
linux,code = <BTN_DPAD_RIGHT>;
|
||||
};
|
||||
sw5 {
|
||||
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
label = "BTN-A";
|
||||
linux,code = <BTN_EAST>;
|
||||
};
|
||||
sw6 {
|
||||
gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
label = "BTN-B";
|
||||
linux,code = <BTN_SOUTH>;
|
||||
};
|
||||
sw7 {
|
||||
gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
label = "BTN-Y";
|
||||
linux,code = <BTN_WEST>;
|
||||
};
|
||||
sw8 {
|
||||
gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
label = "BTN-X";
|
||||
linux,code = <BTN_NORTH>;
|
||||
};
|
||||
sw9 {
|
||||
gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
label = "F1";
|
||||
linux,code = <BTN_TRIGGER_HAPPY1>;
|
||||
};
|
||||
sw10 {
|
||||
gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
|
||||
label = "F2";
|
||||
linux,code = <BTN_TRIGGER_HAPPY2>;
|
||||
};
|
||||
sw11 {
|
||||
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
label = "F3";
|
||||
linux,code = <BTN_TRIGGER_HAPPY3>;
|
||||
};
|
||||
sw12 {
|
||||
gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
|
||||
label = "F4";
|
||||
linux,code = <BTN_TRIGGER_HAPPY4>;
|
||||
};
|
||||
sw13 {
|
||||
gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
label = "F5";
|
||||
linux,code = <BTN_TRIGGER_HAPPY5>;
|
||||
};
|
||||
sw14 {
|
||||
gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
label = "F6";
|
||||
linux,code = <BTN_TRIGGER_HAPPY6>;
|
||||
};
|
||||
sw15 {
|
||||
gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
label = "TOP-LEFT";
|
||||
linux,code = <BTN_TL>;
|
||||
};
|
||||
sw16 {
|
||||
gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
label = "TOP-RIGHT";
|
||||
linux,code = <BTN_TR>;
|
||||
};
|
||||
};
|
||||
|
||||
leds: gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blue_led_pin>;
|
||||
|
||||
blue_led: led-0 {
|
||||
label = "blue:heartbeat";
|
||||
gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
rk817-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "Analog";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Mic Jack",
|
||||
"Headphone", "Headphones",
|
||||
"Speaker", "Speaker";
|
||||
simple-audio-card,routing =
|
||||
"MICL", "Mic Jack",
|
||||
"Headphones", "HPOL",
|
||||
"Headphones", "HPOR",
|
||||
"Speaker", "SPKO";
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk817>;
|
||||
};
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_2ch>;
|
||||
};
|
||||
};
|
||||
|
||||
vccsys: vccsys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v8_sys";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3800000>;
|
||||
regulator-max-microvolt = <3800000>;
|
||||
};
|
||||
|
||||
vcc_host: vcc_host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&usb_midu>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cru {
|
||||
assigned-clocks = <&cru PLL_NPLL>,
|
||||
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
|
||||
<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
|
||||
<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
|
||||
<&cru PLL_CPLL>;
|
||||
|
||||
assigned-clock-rates = <1188000000>,
|
||||
<200000000>, <200000000>,
|
||||
<150000000>, <150000000>,
|
||||
<100000000>, <200000000>,
|
||||
<17000000>;
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
mipi_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mipi_out_panel: endpoint {
|
||||
remote-endpoint = <&mipi_in_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel@0 {
|
||||
compatible = "elida,kd35t133";
|
||||
reg = <0>;
|
||||
backlight = <&backlight>;
|
||||
iovcc-supply = <&vcc_lcd>;
|
||||
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
rotation = <270>;
|
||||
vdd-supply = <&vcc_lcd>;
|
||||
|
||||
port {
|
||||
mipi_in_panel: endpoint {
|
||||
remote-endpoint = <&mipi_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_logic>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-falling-time-ns = <16>;
|
||||
i2c-scl-rising-time-ns = <280>;
|
||||
status = "okay";
|
||||
|
||||
rk817: pmic@20 {
|
||||
compatible = "rockchip,rk817";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-output-names = "rk808-clkout1", "xin32k";
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru SCLK_I2S1_OUT>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
vcc1-supply = <&vccsys>;
|
||||
vcc2-supply = <&vccsys>;
|
||||
vcc3-supply = <&vccsys>;
|
||||
vcc4-supply = <&vccsys>;
|
||||
vcc5-supply = <&vccsys>;
|
||||
vcc6-supply = <&vccsys>;
|
||||
vcc7-supply = <&vccsys>;
|
||||
vcc8-supply = <&vccsys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_arm: DCDC_REG2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: DCDC_REG4 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: LDO_REG2 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v0: LDO_REG3 {
|
||||
regulator-name = "vdd_1v0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG4 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd: LDO_REG6 {
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_bl: LDO_REG7 {
|
||||
regulator-name = "vcc_bl";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_lcd: LDO_REG8 {
|
||||
regulator-name = "vcc_lcd";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <2800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_cam: LDO_REG9 {
|
||||
regulator-name = "vcc_cam";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_midu: BOOST {
|
||||
regulator-name = "usb_midu";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5400000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
rk817_codec: codec {
|
||||
rockchip,mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* I2S 1 Channel Used */
|
||||
&i2s1_2ch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
vccio1-supply = <&vcc_3v3>;
|
||||
vccio2-supply = <&vccio_sd>;
|
||||
vccio3-supply = <&vcc_3v3>;
|
||||
vccio4-supply = <&vcc_3v3>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sfc {
|
||||
pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <108000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy {
|
||||
status = "okay";
|
||||
|
||||
u2phy_host: host-port {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
u2phy_otg: otg-port {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&usb20_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer &uart1_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2m1_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
btns {
|
||||
btn_pins: btn-pins {
|
||||
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
headphone {
|
||||
hp_det: hp-det {
|
||||
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
blue_led_pin: blue-led-pin {
|
||||
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
dc_det: dc-det {
|
||||
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
soc_slppin_gpio: soc_slppin_gpio {
|
||||
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
soc_slppin_rst: soc_slppin_rst {
|
||||
rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
soc_slppin_slp: soc_slppin_slp {
|
||||
rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -33,12 +33,6 @@
|
||||
};
|
||||
|
||||
&binman {
|
||||
simple-bin {
|
||||
fit {
|
||||
offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
|
||||
simple-bin-spi {
|
||||
fit {
|
||||
|
||||
6
arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
Normal file
6
arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
Normal file
@@ -0,0 +1,6 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 ArmSoM Technology Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "rk3588-u-boot.dtsi"
|
||||
37
arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
Normal file
37
arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
Normal file
@@ -0,0 +1,37 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
|
||||
*/
|
||||
|
||||
#include "rk3588-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
||||
};
|
||||
};
|
||||
|
||||
&emmc_pwrseq {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_reset {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
/* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */
|
||||
/delete-property/ mmc-ddr-1_8v;
|
||||
/delete-property/ cap-mmc-highspeed;
|
||||
};
|
||||
|
||||
&uart2m2_xfer {
|
||||
bootph-all;
|
||||
};
|
||||
@@ -4,77 +4,3 @@
|
||||
*/
|
||||
|
||||
#include "rk3588s-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
usb_host1_xhci: usb@fc400000 {
|
||||
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xfc400000 0x0 0x400000>;
|
||||
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
|
||||
<&cru ACLK_USB3OTG1>;
|
||||
clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
||||
dr_mode = "otg";
|
||||
phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
phy_type = "utmi_wide";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
resets = <&cru SRST_A_USB3OTG1>;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u2-freeclk-exists-quirk;
|
||||
snps,dis-del-phy-power-chg-quirk;
|
||||
snps,dis-tx-ipgap-linecheck-quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbdpphy1_grf: syscon@fd5cc000 {
|
||||
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
reg = <0x0 0xfd5cc000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usb2phy1_grf: syscon@fd5d4000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d4000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy1: usb2phy@4000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x4000 0x10>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy1";
|
||||
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy1_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usbdp_phy1: phy@fed90000 {
|
||||
compatible = "rockchip,rk3588-usbdp-phy";
|
||||
reg = <0x0 0xfed90000 0x0 0x10000>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
<&cru CLK_USBDP_PHY1_IMMORTAL>,
|
||||
<&cru PCLK_USBDPPHY1>,
|
||||
<&u2phy1>;
|
||||
clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
||||
<&cru SRST_P_USBDPPHY1>;
|
||||
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
rockchip,u2phy-grf = <&usb2phy1_grf>;
|
||||
rockchip,usb-grf = <&usb_grf>;
|
||||
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -19,95 +19,10 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
usb_host0_xhci: usb@fc000000 {
|
||||
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xfc000000 0x0 0x400000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
|
||||
<&cru ACLK_USB3OTG0>;
|
||||
clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
||||
dr_mode = "otg";
|
||||
phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
phy_type = "utmi_wide";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
resets = <&cru SRST_A_USB3OTG0>;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
snps,dis-u2-freeclk-exists-quirk;
|
||||
snps,dis-del-phy-power-chg-quirk;
|
||||
snps,dis-tx-ipgap-linecheck-quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vo0_grf: syscon@fd5a6000 {
|
||||
compatible = "rockchip,rk3588-vo-grf", "syscon";
|
||||
reg = <0x0 0xfd5a6000 0x0 0x2000>;
|
||||
clocks = <&cru PCLK_VO0GRF>;
|
||||
};
|
||||
|
||||
usb_grf: syscon@fd5ac000 {
|
||||
compatible = "rockchip,rk3588-usb-grf", "syscon";
|
||||
reg = <0x0 0xfd5ac000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usbdpphy0_grf: syscon@fd5c8000 {
|
||||
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usb2phy0_grf: syscon@fd5d0000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d0000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy0: usb2phy@0 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x0 0x10>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy0";
|
||||
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy0_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rng: rng@fe378000 {
|
||||
compatible = "rockchip,trngv1";
|
||||
reg = <0x0 0xfe378000 0x0 0x200>;
|
||||
};
|
||||
|
||||
usbdp_phy0: phy@fed80000 {
|
||||
compatible = "rockchip,rk3588-usbdp-phy";
|
||||
reg = <0x0 0xfed80000 0x0 0x10000>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
<&cru CLK_USBDP_PHY0_IMMORTAL>,
|
||||
<&cru PCLK_USBDPPHY0>,
|
||||
<&u2phy0>;
|
||||
clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
|
||||
<&cru SRST_USBDP_COMBO_PHY0_CMN>,
|
||||
<&cru SRST_USBDP_COMBO_PHY0_LANE>,
|
||||
<&cru SRST_USBDP_COMBO_PHY0_PCS>,
|
||||
<&cru SRST_P_USBDPPHY0>;
|
||||
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
rockchip,u2phy-grf = <&usb2phy0_grf>;
|
||||
rockchip,usb-grf = <&usb_grf>;
|
||||
rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
|
||||
|
||||
@@ -3,6 +3,7 @@ if ARCH_ROCKCHIP
|
||||
config ROCKCHIP_PX30
|
||||
bool "Support Rockchip PX30"
|
||||
select ARM64
|
||||
imply OF_UPSTREAM
|
||||
select SUPPORT_SPL
|
||||
select SUPPORT_TPL
|
||||
select SPL
|
||||
|
||||
@@ -161,6 +161,31 @@ config TARGET_ROCK5B_RK3588
|
||||
USB PD over USB Type-C
|
||||
Size: 100mm x 72mm (Pico-ITX form factor)
|
||||
|
||||
config TARGET_SIGE7_RK3588
|
||||
bool "ArmSoM Sige7 RK3588 board"
|
||||
select BOARD_LATE_INIT
|
||||
help
|
||||
ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer)
|
||||
by ArmSoM.
|
||||
|
||||
There are two variants depending on the DRAM size : 8G and 16G.
|
||||
|
||||
Specification:
|
||||
|
||||
Rockchip Rk3588 SoC
|
||||
4x ARM Cortex-A76, 4x ARM Cortex-A55
|
||||
8/16GB memory LPDDR4x
|
||||
Mali G610MC4 GPU
|
||||
2x MIPI CSI 2 multiple lanes connector
|
||||
64GB/128GB on board eMMC
|
||||
uSD slot
|
||||
1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C
|
||||
1x HDMI 2.1 output
|
||||
2x 2.5 Gbps Ethernet port
|
||||
40-pin IO header including UART, SPI and I2C
|
||||
USB PD over USB Type-C
|
||||
Size: 92mm x 62mm
|
||||
|
||||
config TARGET_QUARTZPRO64_RK3588
|
||||
bool "Pine64 QuartzPro64 RK3588 board"
|
||||
select BOARD_LATE_INIT
|
||||
@@ -168,6 +193,36 @@ config TARGET_QUARTZPRO64_RK3588
|
||||
Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
|
||||
Computer) by Pine64.
|
||||
|
||||
config TARGET_TIGER_RK3588
|
||||
bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)"
|
||||
select BOARD_LATE_INIT
|
||||
help
|
||||
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
|
||||
connector) system-on-module from Theobroma Systems, featuring the
|
||||
Rockchip RK3588.
|
||||
|
||||
It provides the following feature set:
|
||||
* up to 16GB LPDDR4x
|
||||
* on-module eMMC
|
||||
* SD card (on a baseboard) via edge connector
|
||||
* Gigabit Ethernet with on-module GbE PHY
|
||||
* HDMI/eDP
|
||||
* MIPI-DSI
|
||||
* 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
|
||||
* HDMI input over FPC connector
|
||||
* CAN
|
||||
* USB
|
||||
- 1x USB 3.0 dual-role (direct connection)
|
||||
- 2x USB 3.0 host + 1x USB 2.0 host
|
||||
* PCIe
|
||||
- 1x PCIe 2.1 Gen3, 4 lanes
|
||||
- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
|
||||
* on-module ATtiny816 companion controller, implementing:
|
||||
- low-power RTC functionality (ISL1208 emulation)
|
||||
- fan controller (AMC6821 emulation)
|
||||
* on-module Secure Element with Global Platform 2.2.1 compliant
|
||||
JavaCard environment
|
||||
|
||||
config TARGET_TURINGRK1_RK3588
|
||||
bool "Turing Machines RK1 RK3588 board"
|
||||
select BOARD_LATE_INIT
|
||||
@@ -230,6 +285,7 @@ config ROCKCHIP_COMMON_STACK_ADDR
|
||||
config TEXT_BASE
|
||||
default 0x00a00000
|
||||
|
||||
source "board/armsom/sige7-rk3588/Kconfig"
|
||||
source "board/edgeble/neural-compute-module-6/Kconfig"
|
||||
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
|
||||
source "board/indiedroid/nova/Kconfig"
|
||||
@@ -240,5 +296,6 @@ source "board/radxa/rock5b-rk3588/Kconfig"
|
||||
source "board/rockchip/evb_rk3588/Kconfig"
|
||||
source "board/rockchip/toybrick_rk3588/Kconfig"
|
||||
source "board/theobroma-systems/jaguar_rk3588/Kconfig"
|
||||
source "board/theobroma-systems/tiger_rk3588/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
12
board/armsom/sige7-rk3588/Kconfig
Normal file
12
board/armsom/sige7-rk3588/Kconfig
Normal file
@@ -0,0 +1,12 @@
|
||||
if TARGET_SIGE7_RK3588
|
||||
|
||||
config SYS_BOARD
|
||||
default "sige7-rk3588"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "armsom"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "sige7-rk3588"
|
||||
|
||||
endif
|
||||
7
board/armsom/sige7-rk3588/MAINTAINERS
Normal file
7
board/armsom/sige7-rk3588/MAINTAINERS
Normal file
@@ -0,0 +1,7 @@
|
||||
SIGE7-RK3588
|
||||
M: Jianfeng Liu <liujianfeng1994@gmail.com>
|
||||
S: Maintained
|
||||
F: board/armsom/sige7-rk3588
|
||||
F: include/configs/sige7-rk3588.h
|
||||
F: configs/sige7-rk3588_defconfig
|
||||
F: arch/arm/dts/rk3588-armsom-sige7*
|
||||
16
board/theobroma-systems/tiger_rk3588/Kconfig
Normal file
16
board/theobroma-systems/tiger_rk3588/Kconfig
Normal file
@@ -0,0 +1,16 @@
|
||||
if TARGET_TIGER_RK3588
|
||||
|
||||
config SYS_BOARD
|
||||
default "tiger_rk3588"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "theobroma-systems"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "tiger_rk3588"
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select ENV_IS_NOWHERE
|
||||
|
||||
endif
|
||||
13
board/theobroma-systems/tiger_rk3588/MAINTAINERS
Normal file
13
board/theobroma-systems/tiger_rk3588/MAINTAINERS
Normal file
@@ -0,0 +1,13 @@
|
||||
TIGER-RK3588 (SOM-RK3588-Q7)
|
||||
M: Klaus Goger <klaus.goger@cherry.de>
|
||||
M: Quentin Schulz <quentin.schulz@cherry.de>
|
||||
M: Heiko Stuebner <heiko.stuebner@cherry.de>
|
||||
S: Maintained
|
||||
F: board/theobroma-systems/tiger_rk3588
|
||||
F: board/theobroma-systems/common
|
||||
F: doc/board/theobroma-systems/
|
||||
F: include/configs/tiger_rk3588.h
|
||||
F: arch/arm/dts/rk3588-tiger*
|
||||
F: configs/tiger-rk3588_defconfig
|
||||
W: https://embedded.cherry.de/product/tiger-som-rk3588-q7/
|
||||
T: git git://git.embedded.cherry.de/tiger-u-boot.git
|
||||
10
board/theobroma-systems/tiger_rk3588/Makefile
Normal file
10
board/theobroma-systems/tiger_rk3588/Makefile
Normal file
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += tiger_rk3588.o
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
obj-y += ../common/common.o
|
||||
endif
|
||||
53
board/theobroma-systems/tiger_rk3588/tiger_rk3588.c
Normal file
53
board/theobroma-systems/tiger_rk3588/tiger_rk3588.c
Normal file
@@ -0,0 +1,53 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH
|
||||
*/
|
||||
|
||||
#include <phy.h>
|
||||
#include <eth_phy.h>
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/arch-rockchip/cru_rk3588.h>
|
||||
#include <asm/arch-rockchip/hardware.h>
|
||||
#include <asm/arch-rockchip/ioc_rk3588.h>
|
||||
#include <asm-generic/u-boot.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass-id.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#include "../common/common.h"
|
||||
|
||||
#define GPIO2C3_SEL_MASK GENMASK(15, 12)
|
||||
#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1)
|
||||
|
||||
#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15)
|
||||
#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1)
|
||||
#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8)
|
||||
#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1)
|
||||
|
||||
#define REFCLKO25M_ETH0_OUT_EN BIT(4)
|
||||
|
||||
void setup_eth0refclko(void)
|
||||
{
|
||||
/* Configure and enable ETH0_REFCLKO_25MHz */
|
||||
static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
|
||||
static struct rk3588_cru * const cru = (void *)CRU_BASE;
|
||||
|
||||
/* 1. Pinmux */
|
||||
rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M);
|
||||
/* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */
|
||||
rk_clrsetreg(&cru->clksel_con[15],
|
||||
REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK,
|
||||
REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60));
|
||||
/* 3. Enable clock */
|
||||
rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN);
|
||||
}
|
||||
|
||||
int rockchip_early_misc_init_r(void)
|
||||
{
|
||||
setup_boottargets();
|
||||
|
||||
setup_eth0refclko();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -2,27 +2,15 @@ CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00200000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-evb"
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-evb"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
|
||||
CONFIG_TARGET_EVB_PX30=y
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_BASE=0xff178000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_DEBUG_UART=y
|
||||
@@ -39,9 +27,9 @@ CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
@@ -63,7 +51,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
|
||||
@@ -2,27 +2,15 @@ CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00200000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-firefly"
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
|
||||
CONFIG_TARGET_EVB_PX30=y
|
||||
CONFIG_DEBUG_UART_CHANNEL=1
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
@@ -64,6 +52,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
# CONFIG_OF_UPSTREAM is not set
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
@@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x2000
|
||||
CONFIG_ENV_SIZE=0x1f000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar"
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
|
||||
|
||||
@@ -2,29 +2,17 @@ CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00200000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
|
||||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_OFFSET=0x4000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2"
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3326-odroid-go2"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
|
||||
CONFIG_TARGET_ODROID_GO2=y
|
||||
CONFIG_DEBUG_UART_CHANNEL=1
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
@@ -44,11 +32,11 @@ CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
|
||||
@@ -6,7 +6,6 @@ CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_SIZE=0x3000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-puma-haikou"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
@@ -29,7 +28,12 @@ CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_TPL=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_CMD_VBE is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
@@ -41,6 +45,8 @@ CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EROFS=y
|
||||
CONFIG_CMD_SQUASHFS=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
|
||||
@@ -2,27 +2,15 @@ CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00200000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-ctouch2-of10"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
|
||||
CONFIG_TARGET_PX30_CORE=y
|
||||
CONFIG_DEBUG_UART_CHANNEL=1
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
|
||||
@@ -2,27 +2,15 @@ CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00200000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-ctouch2"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
|
||||
CONFIG_TARGET_PX30_CORE=y
|
||||
CONFIG_DEBUG_UART_CHANNEL=1
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
|
||||
@@ -2,27 +2,15 @@ CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00200000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-edimm2.2"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
|
||||
CONFIG_TARGET_PX30_CORE=y
|
||||
CONFIG_DEBUG_UART_CHANNEL=1
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
@@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
|
||||
@@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-ringneck-haikou"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
|
||||
@@ -14,18 +14,18 @@ CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFF030000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_TPL_MAX_SIZE=0x20000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_BOOTSTD_FULL=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x0
|
||||
CONFIG_SPL_PAD_TO=0x38000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
@@ -34,12 +34,15 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_CMD_VBE is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
@@ -47,9 +50,11 @@ CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EROFS=y
|
||||
CONFIG_CMD_SQUASHFS=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
|
||||
93
configs/sige7-rk3588_defconfig
Normal file
93
configs/sige7-rk3588_defconfig
Normal file
@@ -0,0 +1,93 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-armsom-sige7"
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_TARGET_SIGE7_RK3588=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-armsom-sige7.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_ROCKUSB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_AHCI_PCI=y
|
||||
CONFIG_DWC_AHCI=y
|
||||
CONFIG_SPL_CLK=y
|
||||
# CONFIG_USB_FUNCTION_FASTBOOT is not set
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_RTL8169=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_USBDP=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_SPL_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
CONFIG_USB_ETHER_LAN75XX=y
|
||||
CONFIG_USB_ETHER_LAN78XX=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_FUNCTION_ROCKUSB=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
113
configs/tiger-rk3588_defconfig
Normal file
113
configs/tiger-rk3588_defconfig
Normal file
@@ -0,0 +1,113 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x2000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-tiger-haikou"
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_TARGET_TIGER_RK3588=y
|
||||
CONFIG_DEBUG_UART_BASE=0xfeb50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
# CONFIG_DEBUG_UART_BOARD_INIT is not set
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_BOOTMETH_VBE is not set
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-tiger-haikou.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_CYCLIC=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
CONFIG_CMD_ADC=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_SF is not set
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_MII is not set
|
||||
# CONFIG_CMD_BLOCK_CACHE is not set
|
||||
# CONFIG_CMD_EFICONFIG is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EROFS=y
|
||||
CONFIG_CMD_SQUASHFS=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
# CONFIG_OF_TAG_MIGRATE is not set
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_BUTTON=y
|
||||
CONFIG_BUTTON_GPIO=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_GPIO=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_SPL_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_SPL_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
# CONFIG_SPI_FLASH is not set
|
||||
CONFIG_SF_DEFAULT_BUS=5
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_USBDP=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
@@ -119,6 +119,7 @@ List of mainline supported Rockchip boards:
|
||||
- Radxa ROCK 3 Model A (rock-3a-rk3568)
|
||||
|
||||
* rk3588
|
||||
- ArmSoM Sige7 (sige7-rk3588)
|
||||
- Rockchip EVB (evb-rk3588)
|
||||
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
|
||||
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
|
||||
@@ -130,6 +131,7 @@ List of mainline supported Rockchip boards:
|
||||
- Radxa ROCK 5B (rock5b-rk3588)
|
||||
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
|
||||
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
|
||||
- Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588)
|
||||
- Turing Machines RK1 (turing-rk1-rk3588)
|
||||
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
|
||||
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
|
||||
|
||||
@@ -9,3 +9,4 @@ Theobroma Systems
|
||||
jaguar_rk3588
|
||||
puma_rk3399
|
||||
ringneck_px30
|
||||
tiger_rk3588
|
||||
|
||||
102
doc/board/theobroma-systems/tiger_rk3588.rst
Normal file
102
doc/board/theobroma-systems/tiger_rk3588.rst
Normal file
@@ -0,0 +1,102 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
SOM-RK3588-Q7 Tiger
|
||||
===================
|
||||
|
||||
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
|
||||
connector) system-on-module from Theobroma Systems, featuring the
|
||||
Rockchip RK3588.
|
||||
|
||||
It provides the following feature set:
|
||||
* up to 16GB LPDDR4x
|
||||
* on-module eMMC
|
||||
* SD card (on a baseboard) via edge connector
|
||||
* Gigabit Ethernet with on-module GbE PHY
|
||||
* HDMI/eDP
|
||||
* MIPI-DSI
|
||||
* 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
|
||||
* HDMI input over FPC connector
|
||||
* CAN
|
||||
* USB
|
||||
- 1x USB 3.0 dual-role (direct connection)
|
||||
- 2x USB 3.0 host + 1x USB 2.0 host
|
||||
* PCIe
|
||||
- 1x PCIe 2.1 Gen3, 4 lanes
|
||||
- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
|
||||
* on-module ATtiny816 companion controller, implementing:
|
||||
- low-power RTC functionality (ISL1208 emulation)
|
||||
- fan controller (AMC6821 emulation)
|
||||
* on-module Secure Element with Global Platform 2.2.1 compliant
|
||||
JavaCard environment
|
||||
|
||||
Here is the step-by-step to boot to U-Boot on SOM-RK3588-Q7 Tiger from Theobroma
|
||||
Systems.
|
||||
|
||||
Get the TF-A and DDR init (TPL) binaries
|
||||
----------------------------------------
|
||||
|
||||
.. prompt:: bash
|
||||
|
||||
git clone https://github.com/rockchip-linux/rkbin
|
||||
cd rkbin
|
||||
export RKBIN=$(pwd)
|
||||
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf
|
||||
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin
|
||||
sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
|
||||
sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt
|
||||
./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL"
|
||||
./tools/boot_merger RKBOOT/RK3588MINIALL.ini
|
||||
export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
|
||||
|
||||
This will setup all required external dependencies for compiling U-Boot. This will
|
||||
be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot
|
||||
gains support for open-source DRAM initialization in TPL.
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
||||
.. prompt:: bash
|
||||
|
||||
cd ../u-boot
|
||||
make CROSS_COMPILE=aarch64-linux-gnu- tiger-rk3588_defconfig all
|
||||
|
||||
This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
|
||||
(eMMC or SD card).
|
||||
|
||||
Flash the image
|
||||
---------------
|
||||
|
||||
Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC.
|
||||
|
||||
SD-Card
|
||||
~~~~~~~
|
||||
|
||||
.. prompt:: bash
|
||||
|
||||
dd if=u-boot-rockchip.bin of=/dev/sdX seek=64
|
||||
|
||||
.. note::
|
||||
|
||||
Replace ``/dev/sdX`` to match your SD card kernel device.
|
||||
|
||||
eMMC
|
||||
~~~~
|
||||
|
||||
``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface
|
||||
with help of the Rockchip loader binary.
|
||||
|
||||
To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a
|
||||
micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into
|
||||
``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch
|
||||
back to ``Normal Boot`` mode. A new USB device should have appeared on your PC
|
||||
(check with ``lsusb -d 2207:350b``).
|
||||
|
||||
To flash U-Boot on the eMMC with ``rkdeveloptool``:
|
||||
|
||||
.. prompt:: bash
|
||||
|
||||
git clone https://github.com/rockchip-linux/rkdeveloptool
|
||||
cd rkdeveloptool
|
||||
autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make
|
||||
./rkdeveloptool db "$RKDB"
|
||||
./rkdeveloptool wl 64 ../u-boot-rockchip.bin
|
||||
@@ -6,6 +6,7 @@
|
||||
|
||||
#include <dm.h>
|
||||
#include <dm/lists.h>
|
||||
#include <bitfield.h>
|
||||
#include <errno.h>
|
||||
#include <log.h>
|
||||
#include <linux/bitfield.h>
|
||||
@@ -277,10 +278,9 @@ static int rk8xx_probe(struct udevice *dev)
|
||||
return ret;
|
||||
|
||||
priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
|
||||
show_variant = priv->variant;
|
||||
show_variant = bitfield_extract_by_mask(priv->variant, RK8XX_ID_MSK);
|
||||
switch (priv->variant) {
|
||||
case RK808_ID:
|
||||
show_variant = 0x808; /* RK808 hardware ID is 0 */
|
||||
break;
|
||||
case RK805_ID:
|
||||
case RK816_ID:
|
||||
@@ -311,7 +311,7 @@ static int rk8xx_probe(struct udevice *dev)
|
||||
init_data_num = ARRAY_SIZE(rk806_init_reg);
|
||||
break;
|
||||
default:
|
||||
printf("Unknown PMIC: RK%x!!\n", priv->variant);
|
||||
printf("Unknown PMIC: RK%x!!\n", show_variant);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
721
dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
Normal file
721
dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
Normal file
@@ -0,0 +1,721 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "rk3588.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ArmSoM Sige7";
|
||||
compatible = "armsom,sige7", "rockchip,rk3588";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
analog-sound {
|
||||
compatible = "audio-graph-card";
|
||||
dais = <&i2s0_8ch_p0>;
|
||||
label = "rk3588-es8316";
|
||||
hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hp_detect>;
|
||||
routing = "MIC2", "Mic Jack",
|
||||
"Headphones", "HPOL",
|
||||
"Headphones", "HPOR";
|
||||
widgets = "Microphone", "Mic Jack",
|
||||
"Headphone", "Headphones";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_rgb_g>;
|
||||
|
||||
led_green: led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led_red: led-1 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <0 95 145 195 255>;
|
||||
fan-supply = <&vcc5v0_sys>;
|
||||
pwms = <&pwm1 0 50000 0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie2x1l2";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v1_nldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2_psu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0m2_xfer>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu_big0_s0: regulator@42 {
|
||||
compatible = "rockchip,rk8602";
|
||||
reg = <0x42>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu_big0_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_big1_s0: regulator@43 {
|
||||
compatible = "rockchip,rk8603", "rockchip,rk8602";
|
||||
reg = <0x43>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu_big1_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hym8563";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
|
||||
es8316: audio-codec@11 {
|
||||
compatible = "everest,es8316";
|
||||
reg = <0x11>;
|
||||
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
clocks = <&cru I2S0_8CH_MCLKOUT>;
|
||||
clock-names = "mclk";
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
port {
|
||||
es8316_p0_0: endpoint {
|
||||
remote-endpoint = <&i2s0_8ch_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s0_8ch {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_lrck
|
||||
&i2s0_mclk
|
||||
&i2s0_sclk
|
||||
&i2s0_sdi0
|
||||
&i2s0_sdo0>;
|
||||
status = "okay";
|
||||
|
||||
i2s0_8ch_p0: port {
|
||||
i2s0_8ch_p0_0: endpoint {
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
remote-endpoint = <&es8316_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* phy1 - right ethernet port */
|
||||
&pcie2x1l0 {
|
||||
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* phy2 - WiFi */
|
||||
&pcie2x1l1 {
|
||||
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* phy0 - left ethernet port */
|
||||
&pcie2x1l2 {
|
||||
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x4 {
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_rgb_g: led-rgb-g {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
led_rgb_r: led-rgb-r {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
hp_detect: hp-detect {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&avcc_1v8_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
mmc-hs200-1_8v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
max-frequency = <200000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_3v3_s3>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
|
||||
status = "okay";
|
||||
|
||||
pmic@0 {
|
||||
compatible = "rockchip,rk806";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0x0>;
|
||||
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
|
||||
system-power-controller;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc5v0_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcc12-supply = <&vcc5v0_sys>;
|
||||
vcc13-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcc14-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs2_null: dvs2-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs3_null: dvs3-null-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_gpu_s0";
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_lit_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_log_s0: dcdc-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_log_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_vdenc_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_s0: dcdc-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_ddr_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd2_ddr_s3: dcdc-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vdd2_ddr_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_2v0_pldo_s3: dcdc-reg7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_2v0_pldo_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s3: dcdc-reg8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vddq_ddr_s0: dcdc-reg9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vddq_ddr_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s3: dcdc-reg10 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avcc_1v8_s0: pldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "avcc_1v8_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s0: pldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_1v2_s0: pldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-name = "avdd_1v2_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s0: pldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd_s0: pldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vccio_sd_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
pldo6_s3: pldo-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "pldo6_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s3: nldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "vdd_0v75_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_pll_s0: nldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-name = "vdd_ddr_pll_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_0v75_s0: nldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "avdd_0v75_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v85_s0: nldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-name = "vdd_0v85_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s0: nldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "vdd_0v75_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -357,7 +357,7 @@
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
@@ -182,7 +182,7 @@
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
@@ -452,7 +452,7 @@
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
@@ -113,6 +113,16 @@
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_otg: vcc5v0-otg-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&otg_vbus_drv>;
|
||||
regulator-name = "vcc5v0_otg";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
@@ -137,6 +147,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extcon_usb3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -199,6 +213,13 @@
|
||||
<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
otg_vbus_drv: otg-vbus-drv {
|
||||
rockchip,pins =
|
||||
<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
@@ -214,6 +235,23 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
phy-supply = <&vcc5v0_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -231,25 +269,38 @@
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m2_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usbdp_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* host0 on Q7_USB_P2, lower usb3 port */
|
||||
&usbdp_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* host0 on Q7_USB_P2, upper usb3 port */
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* host0 on Q7_USB_P2, lower usb3 port */
|
||||
/* host0 on Q7_USB_P2, upper usb3 port */
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* host0_xhci on Q7_USB_P1, usb3-otg port */
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "otg";
|
||||
extcon = <&extcon_usb3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* host1 on Q7_USB_P3, usb2 port */
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
@@ -260,7 +311,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* host2 on Q7_USB_P2, lower usb3 port */
|
||||
/* host1_xhci on Q7_USB_P0, lower usb3 port */
|
||||
&usb_host1_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* host2 on Q7_USB_P2, upper usb3 port */
|
||||
&usb_host2_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -23,6 +23,14 @@
|
||||
reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
extcon_usb3: extcon-usb3 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb3_id>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
@@ -46,7 +54,7 @@
|
||||
pcie_refclk_gen: pcie-refclk-gen-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
pcie_refclk: pcie-refclk-clock {
|
||||
@@ -139,6 +147,11 @@
|
||||
snps,reset-delays-us = <0 10000 100000>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1m0_xfer>;
|
||||
};
|
||||
@@ -322,6 +335,13 @@
|
||||
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb3 {
|
||||
usb3_id: usb3-id {
|
||||
rockchip,pins =
|
||||
<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
@@ -396,7 +416,7 @@
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
@@ -683,6 +703,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Routed to UART0 on the Q7 connector */
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m2_xfer>;
|
||||
};
|
||||
|
||||
/* Mule-ATtiny UPDI */
|
||||
&uart4 {
|
||||
pinctrl-0 = <&uart4m2_xfer>;
|
||||
|
||||
@@ -318,7 +318,7 @@
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
@@ -7,6 +7,26 @@
|
||||
#include "rk3588-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
usb_host1_xhci: usb@fc400000 {
|
||||
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xfc400000 0x0 0x400000>;
|
||||
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
|
||||
<&cru ACLK_USB3OTG1>;
|
||||
clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
||||
dr_mode = "otg";
|
||||
phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
phy_type = "utmi_wide";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
resets = <&cru SRST_A_USB3OTG1>;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u2-freeclk-exists-quirk;
|
||||
snps,dis-del-phy-power-chg-quirk;
|
||||
snps,dis-tx-ipgap-linecheck-quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie30_phy_grf: syscon@fd5b8000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
||||
@@ -17,6 +37,36 @@
|
||||
reg = <0x0 0xfd5c0000 0x0 0x100>;
|
||||
};
|
||||
|
||||
usbdpphy1_grf: syscon@fd5cc000 {
|
||||
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
reg = <0x0 0xfd5cc000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usb2phy1_grf: syscon@fd5d4000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d4000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy1: usb2phy@4000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x4000 0x10>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy1";
|
||||
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy1_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2s8_8ch: i2s@fddc8000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc8000 0x0 0x1000>;
|
||||
@@ -310,6 +360,28 @@
|
||||
};
|
||||
};
|
||||
|
||||
usbdp_phy1: phy@fed90000 {
|
||||
compatible = "rockchip,rk3588-usbdp-phy";
|
||||
reg = <0x0 0xfed90000 0x0 0x10000>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
<&cru CLK_USBDP_PHY1_IMMORTAL>,
|
||||
<&cru PCLK_USBDPPHY1>,
|
||||
<&u2phy1>;
|
||||
clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
||||
<&cru SRST_P_USBDPPHY1>;
|
||||
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
rockchip,u2phy-grf = <&usb2phy1_grf>;
|
||||
rockchip,usb-grf = <&usb_grf>;
|
||||
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
combphy1_ps: phy@fee10000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee10000 0x0 0x100>;
|
||||
|
||||
@@ -479,7 +479,7 @@
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
@@ -528,7 +528,7 @@
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
@@ -336,7 +336,7 @@
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
@@ -414,7 +414,7 @@
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
@@ -347,6 +347,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
display_subsystem: display-subsystem {
|
||||
compatible = "rockchip,display-subsystem";
|
||||
ports = <&vop_out>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee: optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
@@ -394,11 +399,6 @@
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
display_subsystem: display-subsystem {
|
||||
compatible = "rockchip,display-subsystem";
|
||||
ports = <&vop_out>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
@@ -436,6 +436,84 @@
|
||||
};
|
||||
};
|
||||
|
||||
gpu: gpu@fb000000 {
|
||||
compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
|
||||
reg = <0x0 0xfb000000 0x0 0x200000>;
|
||||
#cooling-cells = <2>;
|
||||
assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
|
||||
<&cru CLK_GPU_STACKS>;
|
||||
clock-names = "core", "coregroup", "stacks";
|
||||
dynamic-power-coefficient = <2982>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
power-domains = <&power RK3588_PD_GPU>;
|
||||
status = "disabled";
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <675000 675000 850000>;
|
||||
};
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <675000 675000 850000>;
|
||||
};
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <675000 675000 850000>;
|
||||
};
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <675000 675000 850000>;
|
||||
};
|
||||
opp-700000000 {
|
||||
opp-hz = /bits/ 64 <700000000>;
|
||||
opp-microvolt = <700000 700000 850000>;
|
||||
};
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <750000 750000 850000>;
|
||||
};
|
||||
opp-900000000 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <800000 800000 850000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <850000 850000 850000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb_host0_xhci: usb@fc000000 {
|
||||
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xfc000000 0x0 0x400000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
|
||||
<&cru ACLK_USB3OTG0>;
|
||||
clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
||||
dr_mode = "otg";
|
||||
phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
phy_type = "utmi_wide";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
resets = <&cru SRST_A_USB3OTG0>;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
snps,dis-u2-freeclk-exists-quirk;
|
||||
snps,dis-del-phy-power-chg-quirk;
|
||||
snps,dis-tx-ipgap-linecheck-quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fc800000 {
|
||||
compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
||||
reg = <0x0 0xfc800000 0x0 0x40000>;
|
||||
@@ -501,6 +579,30 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmu600_pcie: iommu@fc900000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x0 0xfc900000 0x0 0x200000>;
|
||||
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmu600_php: iommu@fcb00000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x0 0xfcb00000 0x0 0x200000>;
|
||||
interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmu1grf: syscon@fd58a000 {
|
||||
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd58a000 0x0 0x10000>;
|
||||
@@ -516,12 +618,23 @@
|
||||
reg = <0x0 0xfd5a4000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
vo0_grf: syscon@fd5a6000 {
|
||||
compatible = "rockchip,rk3588-vo-grf", "syscon";
|
||||
reg = <0x0 0xfd5a6000 0x0 0x2000>;
|
||||
clocks = <&cru PCLK_VO0GRF>;
|
||||
};
|
||||
|
||||
vo1_grf: syscon@fd5a8000 {
|
||||
compatible = "rockchip,rk3588-vo-grf", "syscon";
|
||||
reg = <0x0 0xfd5a8000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_VO1GRF>;
|
||||
};
|
||||
|
||||
usb_grf: syscon@fd5ac000 {
|
||||
compatible = "rockchip,rk3588-usb-grf", "syscon";
|
||||
reg = <0x0 0xfd5ac000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
php_grf: syscon@fd5b0000 {
|
||||
compatible = "rockchip,rk3588-php-grf", "syscon";
|
||||
reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
||||
@@ -537,22 +650,52 @@
|
||||
reg = <0x0 0xfd5c4000 0x0 0x100>;
|
||||
};
|
||||
|
||||
usbdpphy0_grf: syscon@fd5c8000 {
|
||||
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usb2phy0_grf: syscon@fd5d0000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d0000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy0: usb2phy@0 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x0 0x10>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy0";
|
||||
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy0_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb2phy2_grf: syscon@fd5d8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d8000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy2: usb2-phy@8000 {
|
||||
u2phy2: usb2phy@8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x8000 0x10>;
|
||||
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy2";
|
||||
#clock-cells = <0>;
|
||||
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy2_host: host-port {
|
||||
@@ -568,16 +711,16 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy3: usb2-phy@c000 {
|
||||
u2phy3: usb2phy@c000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0xc000 0x10>;
|
||||
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy3";
|
||||
#clock-cells = <0>;
|
||||
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy3_host: host-port {
|
||||
@@ -646,74 +789,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vop: vop@fdd90000 {
|
||||
compatible = "rockchip,rk3588-vop";
|
||||
reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
|
||||
reg-names = "vop", "gamma-lut";
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_VOP>,
|
||||
<&cru HCLK_VOP>,
|
||||
<&cru DCLK_VOP0>,
|
||||
<&cru DCLK_VOP1>,
|
||||
<&cru DCLK_VOP2>,
|
||||
<&cru DCLK_VOP3>,
|
||||
<&cru PCLK_VOP_ROOT>;
|
||||
clock-names = "aclk",
|
||||
"hclk",
|
||||
"dclk_vp0",
|
||||
"dclk_vp1",
|
||||
"dclk_vp2",
|
||||
"dclk_vp3",
|
||||
"pclk_vop";
|
||||
iommus = <&vop_mmu>;
|
||||
power-domains = <&power RK3588_PD_VOP>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,vop-grf = <&vop_grf>;
|
||||
rockchip,vo1-grf = <&vo1_grf>;
|
||||
rockchip,pmu = <&pmu>;
|
||||
status = "disabled";
|
||||
|
||||
vop_out: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vp0: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
vp1: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
vp2: port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
vp3: port@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vop_mmu: iommu@fdd97e00 {
|
||||
compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
|
||||
reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
||||
clock-names = "aclk", "iface";
|
||||
#iommu-cells = <0>;
|
||||
power-domains = <&power RK3588_PD_VOP>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@fd890000 {
|
||||
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfd890000 0x0 0x100>;
|
||||
@@ -1084,6 +1159,87 @@
|
||||
};
|
||||
};
|
||||
|
||||
av1d: video-codec@fdc70000 {
|
||||
compatible = "rockchip,rk3588-av1-vpu";
|
||||
reg = <0x0 0xfdc70000 0x0 0x800>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "vdpu";
|
||||
assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
assigned-clock-rates = <400000000>, <400000000>;
|
||||
clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
clock-names = "aclk", "hclk";
|
||||
power-domains = <&power RK3588_PD_AV1>;
|
||||
resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
|
||||
};
|
||||
|
||||
vop: vop@fdd90000 {
|
||||
compatible = "rockchip,rk3588-vop";
|
||||
reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
|
||||
reg-names = "vop", "gamma-lut";
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_VOP>,
|
||||
<&cru HCLK_VOP>,
|
||||
<&cru DCLK_VOP0>,
|
||||
<&cru DCLK_VOP1>,
|
||||
<&cru DCLK_VOP2>,
|
||||
<&cru DCLK_VOP3>,
|
||||
<&cru PCLK_VOP_ROOT>;
|
||||
clock-names = "aclk",
|
||||
"hclk",
|
||||
"dclk_vp0",
|
||||
"dclk_vp1",
|
||||
"dclk_vp2",
|
||||
"dclk_vp3",
|
||||
"pclk_vop";
|
||||
iommus = <&vop_mmu>;
|
||||
power-domains = <&power RK3588_PD_VOP>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,vop-grf = <&vop_grf>;
|
||||
rockchip,vo1-grf = <&vo1_grf>;
|
||||
rockchip,pmu = <&pmu>;
|
||||
status = "disabled";
|
||||
|
||||
vop_out: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vp0: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
vp1: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
vp2: port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
vp3: port@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vop_mmu: iommu@fdd97e00 {
|
||||
compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
|
||||
reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
||||
clock-names = "aclk", "iface";
|
||||
#iommu-cells = <0>;
|
||||
power-domains = <&power RK3588_PD_VOP>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s4_8ch: i2s@fddc0000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc0000 0x0 0x1000>;
|
||||
@@ -1375,6 +1531,16 @@
|
||||
reg = <0x0 0xfdf82200 0x0 0x20>;
|
||||
};
|
||||
|
||||
dfi: dfi@fe060000 {
|
||||
reg = <0x00 0xfe060000 0x00 0x10000>;
|
||||
compatible = "rockchip,rk3588-dfi";
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
rockchip,pmu = <&pmu1grf>;
|
||||
};
|
||||
|
||||
pcie2x1l1: pcie@fe180000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
bus-range = <0x30 0x3f>;
|
||||
@@ -1477,16 +1643,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
dfi: dfi@fe060000 {
|
||||
reg = <0x00 0xfe060000 0x00 0x10000>;
|
||||
compatible = "rockchip,rk3588-dfi";
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
rockchip,pmu = <&pmu1grf>;
|
||||
};
|
||||
|
||||
gmac1: ethernet@fe1c0000 {
|
||||
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
||||
@@ -2380,6 +2536,28 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbdp_phy0: phy@fed80000 {
|
||||
compatible = "rockchip,rk3588-usbdp-phy";
|
||||
reg = <0x0 0xfed80000 0x0 0x10000>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
<&cru CLK_USBDP_PHY0_IMMORTAL>,
|
||||
<&cru PCLK_USBDPPHY0>,
|
||||
<&u2phy0>;
|
||||
clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
|
||||
<&cru SRST_USBDP_COMBO_PHY0_CMN>,
|
||||
<&cru SRST_USBDP_COMBO_PHY0_LANE>,
|
||||
<&cru SRST_USBDP_COMBO_PHY0_PCS>,
|
||||
<&cru SRST_P_USBDPPHY0>;
|
||||
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
rockchip,u2phy-grf = <&usb2phy0_grf>;
|
||||
rockchip,usb-grf = <&usb_grf>;
|
||||
rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
combphy0_ps: phy@fee00000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee00000 0x0 0x100>;
|
||||
@@ -2487,19 +2665,6 @@
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
av1d: video-codec@fdc70000 {
|
||||
compatible = "rockchip,rk3588-av1-vpu";
|
||||
reg = <0x0 0xfdc70000 0x0 0x800>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "vdpu";
|
||||
assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
assigned-clock-rates = <400000000>, <400000000>;
|
||||
clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
||||
clock-names = "aclk", "hclk";
|
||||
power-domains = <&power RK3588_PD_AV1>;
|
||||
resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "rk3588s-pinctrl.dtsi"
|
||||
|
||||
15
include/configs/sige7-rk3588.h
Normal file
15
include/configs/sige7-rk3588.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2024 ArmSoM Technology Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __SIGE7_RK3588_H
|
||||
#define __SIGE7_RK3588_H
|
||||
|
||||
#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
#include <configs/rk3588_common.h>
|
||||
|
||||
#endif /* __SIGE7_RK3588_H */
|
||||
15
include/configs/tiger_rk3588.h
Normal file
15
include/configs/tiger_rk3588.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
|
||||
*/
|
||||
|
||||
#ifndef __TIGER_RK3588_H
|
||||
#define __TIGER_RK3588_H
|
||||
|
||||
#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
#include <configs/rk3588_common.h>
|
||||
|
||||
#endif /* __TIGER_RK3588_H */
|
||||
Reference in New Issue
Block a user