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Merge branch 'next'

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Note that this undoes the changes of commit cf6d4535cc ("x86:
emulation: Disable bloblist for now") as that was intended only for the
release due to time.
This commit is contained in:
Tom Rini
2025-04-07 16:40:02 -06:00
parent 34820924ed f892a7f397
commit ff61d6bfd1
2220 changed files with 138632 additions and 30229 deletions
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35
.azure-pipelines.yml
View File

@@ -134,8 +134,11 @@ stages:
export USER=azure
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt
pip install -r tools/buildman/requirements.txt
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
-r tools/patman/requirements.txt \
-r tools/u_boot_pylib/requirements.txt
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
@@ -163,9 +166,14 @@ stages:
- script: |
git config --global --add safe.directory $(work_dir)
export USER=azure
pip install -r test/py/requirements.txt
pip install -r tools/buildman/requirements.txt
pip install asteval pylint==2.12.2 pyopenssl
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
-r tools/patman/requirements.txt \
-r tools/u_boot_pylib/requirements.txt \
asteval pylint==3.3.4 pyopenssl
export PATH=${PATH}:~/.local/bin
echo "[MASTER]" >> .pylintrc
echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
@@ -265,7 +273,13 @@ stages:
if [ -n "\${BUILD_ENV}" ]; then
export \${BUILD_ENV};
fi
pip install -r tools/buildman/requirements.txt
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
-r test/py/requirements.txt \
-r tools/u_boot_pylib/requirements.txt \
pytest-azurepipelines
tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
cp /opt/grub/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
@@ -289,10 +303,6 @@ stages:
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt
pip install pytest-azurepipelines
export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
# "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
@@ -582,7 +592,10 @@ stages:
# make environment variables available as tests are running inside a container
export BUILDMAN="${BUILDMAN}"
git config --global --add safe.directory ${WORK_DIR}
pip install -r tools/buildman/requirements.txt
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt
EOF
cat << "EOF" >> build.sh
if [[ "${BUILDMAN}" != "" ]]; then

35
.gitlab-ci.yml
View File

@@ -56,6 +56,11 @@ stages:
wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
export BINMAN_INDIRS=/tmp;
fi
# Prepare python environment
- virtualenv -p /usr/bin/python3 /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
after_script:
- cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
@@ -91,9 +96,6 @@ stages:
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt
# "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
- export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
@@ -121,9 +123,13 @@ build all platforms in a single job:
tags:
- ${HOST}
script:
# Prepare python environment
- virtualenv -p /usr/bin/python3 /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
pip install -r tools/buildman/requirements.txt;
./tools/buildman/buildman -o /tmp -PEWM -x xtensa || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
@@ -180,8 +186,9 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
export USER=gitlab;
virtualenv -p /usr/bin/python3 /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt;
pip install -r tools/buildman/requirements.txt;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
-r tools/u_boot_pylib/requirements.txt;
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
@@ -200,9 +207,11 @@ Run pylint:
extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- pip install -r test/py/requirements.txt
- pip install -r tools/buildman/requirements.txt
- pip install asteval pylint==2.12.2 pyopenssl
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
-r tools/u_boot_pylib/requirements.txt asteval pylint==3.3.4 pyopenssl
- export PATH=${PATH}:~/.local/bin
- echo "[MASTER]" >> .pylintrc
- echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
@@ -556,7 +565,7 @@ coreboot test.py:
- export USE_LABGRID_SJG=1
# export verbose="-v"
- ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}"
--capture=tee-sys -k "not bootstd" || ret=$?
--capture=tee-sys -k "not bootstd ${TEST_PY_TEST_SPEC}" || ret=$?
- U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
- if [[ $ret -ne 0 ]]; then
exit $ret;
@@ -693,3 +702,9 @@ vf2:
variables:
ROLE: vf2
<<: *lab_dfn
qemu-x86_64:
variables:
ROLE: qemu-x86_64
TEST_PY_TEST_SPEC: "and not sleep"
<<: *lab_dfn

13
Kconfig
View File

@@ -27,6 +27,17 @@ config DEPRECATED
code that relies on deprecated features that will be removed and
the conversion deadline has passed.
config WERROR
bool "Compile U-Boot with warnings as errors"
help
A U-Boot build should not cause any compiler warnings, and this
enables the '-Werror' flag to enforce that rule.
However, if you have a new (or very old) compiler or linker with odd
and unusual warnings, or you have some architecture with problems,
you may need to disable this config option in order to
successfully build U-Boot.
config LOCALVERSION
string "Local version - append to U-Boot release"
help
@@ -737,7 +748,7 @@ source "dts/Kconfig"
source "env/Kconfig"
menu Networking
menu "Networking"
choice
prompt "Networking stack"

25
MAINTAINERS
View File

@@ -151,9 +151,11 @@ F: cmd/arm/
ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
M: Tien Fong Chee <tien.fong.chee@intel.com>
M: Tien Fong Chee <tien.fong.chee@altera.com>
M: Tingting Meng <tingting.meng@altera.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
F: drivers/ddr/altera/
F: arch/arm/mach-socfpga/
F: drivers/sysreset/sysreset_socfpga*
@@ -313,6 +315,7 @@ F: board/freescale/*mx*/
F: board/freescale/common/
F: common/spl/spl_imx_container.c
F: doc/imx/
F: drivers/mailbox/imx-mailbox.c
F: drivers/serial/serial_mxc.c
F: include/imx_container.h
@@ -629,11 +632,24 @@ F: arch/arm/mach-sc5xx/
F: board/adi/
F: doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml
F: doc/device-tree-bindings/clock/adi,sc5xx-clocks.yaml
F: doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
F: doc/device-tree-bindings/timer/adi,sc5xx-gptimer.yaml
F: drivers/clk/adi/
F: drivers/dma/adi_dma.c
F: drivers/gpio/adp5588_gpio.c
F: drivers/gpio/gpio-adi-adsp.c
F: drivers/i2c/adi_i2c.c
F: drivers/mmc/adi_sdhci.c
F: drivers/net/dwc_eth_qos_adi.c
F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/remoteproc/adi_sc5xx_rproc.c
F: drivers/serial/serial_adi_uart4.c
F: drivers/spi/adi_spi3.c
F: drivers/timer/adi_sc5xx_timer.c
F: drivers/usb/musb-new/sc5xx.c
F: drivers/watchdog/adi_wdt.c
F: include/configs/sc5*
F: include/dt-bindings/pinctrl/adi-adsp.h
F: include/env/adi/
ARM SNAPDRAGON
@@ -1265,6 +1281,13 @@ T: git git://github.com/ARM-software/u-boot.git
F: drivers/video/mali_dp.c
F: drivers/i2c/i2c-versatile.c
MEMBUF
M: Simon Glass <sjg@chromium.org>
S: Maintained
T: git https://source.denx.de/u-boot/u-boot.git
F: include/membuf.h
F: lib/membuf.c
MICROBLAZE
M: Michal Simek <monstr@monstr.eu>
S: Maintained

23
Makefile
View File

@@ -406,6 +406,7 @@ LDR = $(CROSS_COMPILE)ldr
STRIP = $(CROSS_COMPILE)strip
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
READELF = $(CROSS_COMPILE)readelf
LEX = flex
YACC = bison
AWK = awk
@@ -820,6 +821,7 @@ KBUILD_AFLAGS += $(KAFLAGS)
KBUILD_CFLAGS += $(KCFLAGS)
KBUILD_LDFLAGS += -z noexecstack
KBUILD_LDFLAGS += -z norelro
KBUILD_LDFLAGS += $(call ld-option,--no-warn-rwx-segments)
KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
@@ -878,7 +880,6 @@ libs-y += drivers/usb/dwc3/
libs-y += drivers/usb/common/
libs-y += drivers/usb/emul/
libs-y += drivers/usb/eth/
libs-$(CONFIG_USB_DEVICE) += drivers/usb/gadget/
libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
libs-y += drivers/usb/host/
@@ -893,9 +894,6 @@ ifdef CONFIG_POST
libs-y += post/
endif
libs-$(CONFIG_$(PHASE_)UNIT_TEST) += test/
libs-$(CONFIG_UT_ENV) += test/env/
libs-$(CONFIG_UT_OPTEE) += test/optee/
libs-$(CONFIG_UT_OVERLAY) += test/overlay/
libs-y += $(if $(wildcard $(srctree)/board/$(BOARDDIR)/Makefile),board/$(BOARDDIR)/)
@@ -1019,8 +1017,10 @@ INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi
# Generate this input file for binman
ifeq ($(CONFIG_SPL),)
ifneq ($(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO)),)
INPUTS-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
endif
endif
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
@@ -1067,7 +1067,7 @@ quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) --gap-fill=0xff $(OBJCOPYFLAGS) \
$(OBJCOPYFLAGS_$(@F)) $< $@
# Provide a version which does not do this, for use by EFI
# Provide a version which does not do this, for use by EFI and hex/srec
quiet_cmd_zobjcopy = OBJCOPY $@
cmd_zobjcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
@@ -1282,7 +1282,7 @@ OBJCOPYFLAGS_u-boot.hex := -O ihex
OBJCOPYFLAGS_u-boot.srec := -O srec
u-boot.hex u-boot.srec: u-boot FORCE
$(call if_changed,objcopy)
$(call if_changed,zobjcopy)
OBJCOPYFLAGS_u-boot-elf.srec := $(OBJCOPYFLAGS_u-boot.srec)
@@ -1296,12 +1296,12 @@ OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x50000000
endif
u-boot-elf.srec: u-boot.elf FORCE
$(call if_changed,objcopy)
$(call if_changed,zobjcopy)
OBJCOPYFLAGS_u-boot-spl.srec = $(OBJCOPYFLAGS_u-boot.srec)
spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
$(call if_changed,zobjcopy)
%.scif: %.srec
$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
@@ -1436,7 +1436,7 @@ OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
$(call if_changed,objcopy)
$(call if_changed,zobjcopy)
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
@@ -1865,6 +1865,7 @@ quiet_cmd_gen_envp = ENVP $@
$(CPP) -P $(cpp_flags) -x assembler-with-cpp -undef \
-D__ASSEMBLY__ \
-D__UBOOT_CONFIG__ \
-DDEFAULT_DEVICE_TREE=$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE)) \
-I . -I include -I $(srctree)/include \
-include linux/kconfig.h -include include/config.h \
-I$(srctree)/arch/$(ARCH)/include \
@@ -2176,7 +2177,7 @@ System.map: u-boot
# ARM relocations should all be R_ARM_RELATIVE (32-bit) or
# R_AARCH64_RELATIVE (64-bit).
checkarmreloc: u-boot
@RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \
@RELOC="`$(READELF) -r -W $< | cut -d ' ' -f 4 | \
grep R_A | sort -u`"; \
if test "$$RELOC" != "R_ARM_RELATIVE" -a \
"$$RELOC" != "R_AARCH64_RELATIVE"; then \
@@ -2515,7 +2516,7 @@ cmd_genenv = \
sed -e '/^\s*$$/d' | \
sort -t '=' -k 1,1 -s -o $@
u-boot-initial-env: scripts_basic $(env_h) FORCE
u-boot-initial-env: scripts_basic $(version_h) $(env_h) include/config.h FORCE
$(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv
$(call if_changed,genenv)

2
README
View File

@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000 - 2013
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.

6
arch/arc/lib/cache.c
View File

@@ -8,6 +8,7 @@
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <asm/arcregs.h>
@@ -819,3 +820,8 @@ void sync_n_cleanup_cache_all(void)
__ic_entire_invalidate();
}
int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
return -ENOSYS;
}

16
arch/arm/Kconfig
View File

@@ -600,6 +600,13 @@ choice
prompt "Target select"
default TARGET_HIKEY
config ARCH_AIROHA
bool "Airoha SoCs"
select DM
select OF_CONTROL
help
Support for the Airoha soc.
config ARCH_AT91
bool "Atmel AT91"
select GPIO_EXTRA_HEADER
@@ -648,7 +655,6 @@ config ARCH_MVEBU
select SPL_TIMER if SPL
select TIMER if !ARM64
select OF_CONTROL
select OF_SEPARATE
select SPI
imply CMD_DM
@@ -1110,13 +1116,14 @@ config ARCH_SNAPDRAGON
select GPIO_EXTRA_HEADER
select MSM_SMEM
select OF_CONTROL
select OF_SEPARATE
select SMEM
select SPMI
select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
select SYSRESET
select SYSRESET_PSCI
imply OF_UPSTREAM
imply CMD_DM
@@ -1128,7 +1135,6 @@ config ARCH_SOCFPGA
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
select GICV2
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
@@ -1150,6 +1156,7 @@ config ARCH_SOCFPGA
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
TARGET_SOCFPGA_SOC64
select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
@@ -1185,7 +1192,6 @@ config ARCH_SUNXI
select DM_SERIAL
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
select PINCTRL
select SPECIFY_CONSOLE_INDEX
select SPL_SEPARATE_BSS if SPL
@@ -2251,6 +2257,8 @@ config SYS_KWD_CONFIG
Path within the source directory to the kwbimage.cfg file to use
when packaging the U-Boot image for use.
source "arch/arm/mach-airoha/Kconfig"
source "arch/arm/mach-apple/Kconfig"
source "arch/arm/mach-aspeed/Kconfig"

1
arch/arm/Makefile
View File

@@ -51,6 +51,7 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AIROHA) += airoha
machine-$(CONFIG_ARCH_APPLE) += apple
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91

6
arch/arm/cpu/arm926ejs/cache.c
View File

@@ -5,6 +5,7 @@
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/errno.h>
#include <linux/types.h>
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
@@ -88,3 +89,8 @@ void enable_caches(void)
dcache_enable();
#endif
}
int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
return -ENOSYS;
}

6
arch/arm/cpu/armv7/cache_v7.c
View File

@@ -6,6 +6,7 @@
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <asm/armv7.h>
#include <asm/utils.h>
@@ -209,3 +210,8 @@ __weak void v7_outer_cache_flush_all(void) {}
__weak void v7_outer_cache_inval_all(void) {}
__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
return -ENOSYS;
}

8
arch/arm/cpu/armv7/exception_level.c
View File

@@ -11,9 +11,9 @@
#include <bootm.h>
#include <cpu_func.h>
#include <log.h>
#include <setjmp.h>
#include <asm/armv7.h>
#include <asm/secure.h>
#include <asm/setjmp.h>
/**
* entry_non_secure() - entry point when switching to non-secure mode
@@ -24,7 +24,7 @@
*
* @non_secure_jmp: jump buffer for restoring stack and registers
*/
static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
static void entry_non_secure(jmp_buf non_secure_jmp)
{
dcache_enable();
debug("Reached non-secure mode\n");
@@ -42,10 +42,10 @@ static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
void switch_to_non_secure_mode(void)
{
static bool is_nonsec;
struct jmp_buf_data non_secure_jmp;
jmp_buf non_secure_jmp;
if (armv7_boot_nonsec() && !is_nonsec) {
if (setjmp(&non_secure_jmp))
if (setjmp(non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to HYP */
armv7_init_nonsec();

4
arch/arm/cpu/armv7/lowlevel_init.S
View File

@@ -26,8 +26,8 @@ WEAK(lowlevel_init)
/*
* Setup a temporary stack. Global data is not available yet.
*/
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =CONFIG_SPL_STACK
#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
ldr sp, =CONFIG_VAL(STACK)
#else
ldr sp, =SYS_INIT_SP_ADDR
#endif

4
arch/arm/cpu/armv7/start.S
View File

@@ -279,8 +279,8 @@ ENTRY(cpu_init_cp15)
orr r2, r4, r2 @ r2 has combined CPU variant + revision
/* Early stack for ERRATA that needs into call C code */
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
ldr r0, =CONFIG_VAL(STACK)
#else
ldr r0, =(SYS_INIT_SP_ADDR)
#endif

6
arch/arm/cpu/armv7m/cache.c
View File

@@ -11,6 +11,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/errno.h>
/* Cache maintenance operation registers */
@@ -370,3 +371,8 @@ void enable_caches(void)
dcache_enable();
#endif
}
int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
return -ENOSYS;
}

119
arch/arm/cpu/armv8/cache_v8.c
View File

@@ -14,6 +14,7 @@
#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -421,7 +422,7 @@ static int count_ranges(void)
return count;
}
#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK)
#define ALL_ATTRS (3 << 8 | PMD_ATTRMASK)
#define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3)
enum walker_state {
@@ -568,6 +569,24 @@ static void pretty_print_table_attrs(u64 pte)
static void pretty_print_block_attrs(u64 pte)
{
u64 attrs = pte & PMD_ATTRINDX_MASK;
u64 perm_attrs = pte & PMD_ATTRMASK;
char mem_attrs[16] = { 0 };
int cnt = 0;
if (perm_attrs & PTE_BLOCK_PXN)
cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "PXN ");
if (perm_attrs & PTE_BLOCK_UXN) {
if (get_effective_el() == 1)
cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN ");
else
cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "XN ");
}
if (perm_attrs & PTE_BLOCK_RO)
cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "RO");
if (!mem_attrs[0])
snprintf(mem_attrs, sizeof(mem_attrs), "RWX ");
printf(" | %-10s", mem_attrs);
switch (attrs) {
case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE):
@@ -613,6 +632,7 @@ static void print_pte(u64 pte, int level)
{
if (PTE_IS_TABLE(pte, level)) {
printf(" %-5s", "Table");
printf(" %-12s", "|");
pretty_print_table_attrs(pte);
} else {
pretty_print_pte_type(pte);
@@ -642,9 +662,9 @@ static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int lev
printf("%*s", indent * 2, "");
if (PTE_IS_TABLE(start_attrs, level))
printf("[%#011llx]%14s", _addr, "");
printf("[%#016llx]%19s", _addr, "");
else
printf("[%#011llx - %#011llx]", _addr, end);
printf("[%#016llx - %#016llx]", _addr, end);
printf("%*s | ", (3 - level) * 2, "");
print_pte(start_attrs, level);
@@ -952,6 +972,34 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
flush_dcache_range(real_start, real_start + real_size);
}
void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs)
{
int level;
u64 r, size, start;
/*
* Loop through the address range until we find a page granule that fits
* our alignment constraints and set the new permissions
*/
start = addr;
size = siz;
while (size > 0) {
for (level = 1; level < 4; level++) {
/* Set PTE to new attributes */
r = set_one_region(start, size, attrs, true, level);
if (r) {
/* PTE successfully updated */
size -= r;
start += r;
break;
}
}
}
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
__asm_invalidate_tlb_all();
}
/*
* Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
* The procecess is break-before-make. The target region will be marked as
@@ -986,27 +1034,47 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
gd->arch.tlb_addr + gd->arch.tlb_size);
__asm_invalidate_tlb_all();
/*
* Loop through the address range until we find a page granule that fits
* our alignment constraints, then set it to the new cache attributes
*/
start = addr;
size = siz;
while (size > 0) {
for (level = 1; level < 4; level++) {
/* Set PTE to new attributes */
r = set_one_region(start, size, attrs, true, level);
if (r) {
/* PTE successfully updated */
size -= r;
start += r;
break;
}
}
mmu_change_region_attr_nobreak(addr, siz, attrs);
}
int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE | PTE_TYPE_VALID;
switch (perm) {
case MMU_ATTR_RO:
/*
* get_effective_el() will return 1 if
* - Running in EL1 so we assume an EL1 translation regime
* with HCR_EL2.{NV, NV1} != {1,1}
* - Running in EL2 with HCR_EL2.E2H = 1 so we assume an
* EL2&0 translation regime. Since we don't have accesses
* from EL0 we don't have to check HCR_EL2.TGE
*
* Both of these requires PXN to be set
*/
if (get_effective_el() == 1)
attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO;
else
attrs |= PTE_BLOCK_UXN | PTE_BLOCK_RO;
break;
case MMU_ATTR_RX:
attrs |= PTE_BLOCK_RO;
break;
case MMU_ATTR_RW:
if (get_effective_el() == 1)
attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN;
else
attrs |= PTE_BLOCK_UXN;
break;
default:
log_err("Unknown attribute %d\n", perm);
return -EINVAL;
}
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
__asm_invalidate_tlb_all();
mmu_change_region_attr_nobreak(addr, size, attrs);
return 0;
}
#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
@@ -1112,3 +1180,8 @@ void __weak enable_caches(void)
icache_enable();
dcache_enable();
}
void arch_dump_mem_attrs(void)
{
dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL));
}

8
arch/arm/cpu/armv8/exception_level.c
View File

@@ -11,8 +11,8 @@
#include <bootm.h>
#include <cpu_func.h>
#include <log.h>
#include <setjmp.h>
#include <asm/cache.h>
#include <asm/setjmp.h>
/**
* entry_non_secure() - entry point when switching to non-secure mode
@@ -23,7 +23,7 @@
*
* @non_secure_jmp: jump buffer for restoring stack and registers
*/
static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
static void entry_non_secure(jmp_buf non_secure_jmp)
{
dcache_enable();
debug("Reached non-secure mode\n");
@@ -42,11 +42,11 @@ static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
*/
void switch_to_non_secure_mode(void)
{
struct jmp_buf_data non_secure_jmp;
jmp_buf non_secure_jmp;
/* On AArch64 we need to make sure we call our payload in < EL3 */
if (current_el() == 3) {
if (setjmp(&non_secure_jmp))
if (setjmp(non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to EL2 */

7
arch/arm/cpu/armv8/fel_utils.S
View File

@@ -63,9 +63,12 @@ ENTRY(return_to_fel)
1: wfi
b 1b
fel_stash_addr: // must immediately precede back_in_32:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
/* AArch32 code to restore the state from fel_stash and return back to FEL. */
back_in_32:
.word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
.word 0xe51f000c // ldr r0, [pc, #-12] ; load fel_stash address
.word 0xe5901008 // ldr r1, [r0, #8]
.word 0xe129f001 // msr CPSR_fc, r1
.word 0xf57ff06f // isb
@@ -77,6 +80,4 @@ back_in_32:
.word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
.word 0xe12fff1e // bx lr ; return to FEL
fel_stash_addr:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
ENDPROC(return_to_fel)

13
arch/arm/cpu/armv8/spl_data.c
View File

@@ -5,23 +5,28 @@
#include <spl.h>
char __data_start[0] __section(".__data_start");
char __data_save_start[0] __section(".__data_save_start");
char __data_save_end[0] __section(".__data_save_end");
u32 cold_reboot_flag = 1;
u32 __weak reset_flag(void)
{
return 1;
}
void spl_save_restore_data(void)
{
u32 data_size = __data_save_end - __data_save_start;
cold_reboot_flag = reset_flag();
if (cold_reboot_flag == 1) {
/* Save data section to data_save section */
memcpy(__data_save_start, __data_save_start - data_size,
data_size);
memcpy(__data_save_start, __data_start, data_size);
} else {
/* Restore the data_save section to data section */
memcpy(__data_save_start - data_size, __data_save_start,
data_size);
memcpy(__data_start, __data_save_start, data_size);
}
cold_reboot_flag++;

1
arch/arm/cpu/armv8/u-boot-spl.lds
View File

@@ -37,6 +37,7 @@ SECTIONS
.data : {
. = ALIGN(8);
*(.__data_start)
*(.data*)
} >.sram

61
arch/arm/cpu/armv8/u-boot.lds
View File

@@ -36,9 +36,18 @@ SECTIONS
__efi_runtime_stop = .;
}
#ifdef CONFIG_MMU_PGPROT
.text_rest ALIGN(CONSTANT(COMMONPAGESIZE)) :
#else
.text_rest :
#endif
{
__text_start = .;
*(.text*)
#ifdef CONFIG_MMU_PGPROT
. = ALIGN(CONSTANT(COMMONPAGESIZE));
#endif
__text_end = .;
}
#ifdef CONFIG_ARMV8_PSCI
@@ -97,24 +106,6 @@ SECTIONS
LONG(0x1d1071c); /* Must output something to reset LMA */
}
#endif
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(8);
.data : {
*(.data*)
}
. = ALIGN(8);
. = .;
. = ALIGN(8);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
@@ -122,10 +113,36 @@ SECTIONS
__efi_runtime_rel_stop = .;
}
#ifdef CONFIG_MMU_PGPROT
.rodata ALIGN(CONSTANT(COMMONPAGESIZE)): {
#else
.rodata ALIGN(8) : {
#endif
__start_rodata = .;
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
__u_boot_list ALIGN(8) : {
KEEP(*(SORT(__u_boot_list*)));
#ifdef CONFIG_MMU_PGPROT
. = ALIGN(CONSTANT(COMMONPAGESIZE));
#endif
__end_rodata = .;
}
#ifdef CONFIG_MMU_PGPROT
.data ALIGN(CONSTANT(COMMONPAGESIZE)) : {
#else
.data ALIGN(8) : {
#endif
__start_data = .;
*(.data*)
}
. = ALIGN(8);
__image_copy_end = .;
.rela.dyn : {
.rela.dyn ALIGN(8) : {
__rel_dyn_start = .;
*(.rela*)
__rel_dyn_end = .;
@@ -136,11 +153,15 @@ SECTIONS
/*
* arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0
*/
.bss ALIGN(8) : {
.bss ADDR(.rela.dyn) (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
__bss_end = .;
#ifdef CONFIG_MMU_PGPROT
. = ALIGN(CONSTANT(COMMONPAGESIZE));
#endif
__end_data = .;
}
/DISCARD/ : { *(.dynsym) }

29
arch/arm/cpu/u-boot.lds
View File

@@ -169,15 +169,6 @@ SECTIONS
_end = .;
_image_binary_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
* should not be used by new boards/CPUs.
*/
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
/*
* These sections occupy the same memory, but their lifetimes do
* not overlap: U-Boot initializes .bss only after applying dynamic
@@ -190,14 +181,14 @@ SECTIONS
__bss_end = .;
}
.dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu.hash : { *(.gnu.hash) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynbss) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu.hash) }
/DISCARD/ : { *(.gnu*) }
/DISCARD/ : { *(.ARM.exidx*) }
/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
}

12
arch/arm/dts/Makefile
View File

@@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
tegra30-lg-p880.dtb \
tegra30-lg-p895.dtb \
tegra30-microsoft-surface-rt.dtb \
tegra30-ouya.dtb \
tegra30-tec-ng.dtb \
tegra30-wexler-qc750.dtb \
tegra114-dalmore.dtb \
@@ -121,6 +122,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
tegra124-nyan-big.dtb \
tegra124-cei-tk1-som.dtb \
tegra124-venice2.dtb \
tegra124-xiaomi-mocha.dtb \
tegra186-p2771-0000-000.dtb \
tegra186-p2771-0000-500.dtb \
tegra210-p2371-0000.dtb \
@@ -795,7 +797,6 @@ dtb-y += \
imx6q-icore-rqs.dtb \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
imx6q-lxr.dtb \
imx6q-marsboard.dtb \
imx6q-mccmon6.dtb\
imx6q-nitrogen6x.dtb \
@@ -918,8 +919,7 @@ dtb-$(CONFIG_ARCH_IMX9) += \
imx93-var-som-symphony.dtb \
imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb \
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
dtb-$(CONFIG_RZA1) += \
@@ -1103,17 +1103,19 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
k3-j721e-r5-sk.dtb \
k3-j721e-r5-beagleboneai64.dtb
dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb \
k3-am67a-r5-beagley-ai.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
k3-am642-r5-sk.dtb \

18
arch/arm/dts/an7581-u-boot.dtsi Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
atf-reserved-memory@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x40000>;
};
};
};
&uart1 {
bootph-all;
};

71
arch/arm/dts/at91-sam9x60_curiosity.dts
View File

@@ -82,6 +82,11 @@
};
};
&dbgu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
@@ -171,10 +176,20 @@
&macb0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "okay";
};
&pinctrl {
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
@@ -217,6 +232,22 @@
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
};
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
@@ -240,6 +271,36 @@
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A
(AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */
AT91_PIOA 16 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */
AT91_PIOA 15 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */
AT91_PIOA 18 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */
AT91_PIOA 19 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */
AT91_PIOA 20 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
};
};
sdhci1 {
pinctrl_sdhci1: sdhci1 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
};
};
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
@@ -248,6 +309,16 @@
};
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0>;
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1>;
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0

76
arch/arm/dts/at91sam9260.dtsi
View File

@@ -401,51 +401,11 @@
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x600>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
>;
atmel,mux-mask = <
/* A B */
@@ -767,6 +727,42 @@
atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
};
dbgu: serial@fffff200 {

77
arch/arm/dts/at91sam9261.dtsi
View File

@@ -286,51 +286,12 @@
status = "disabled";
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x600>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
>;
atmel,mux-mask =
/* A B */
<0xffffffff 0xfffffff7>, /* pioA */
@@ -573,6 +534,42 @@
<AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
};
pmc: pmc@fffffc00 {

117
arch/arm/dts/at91sam9263.dtsi
View File

@@ -404,12 +404,6 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff200 0xfffff200 0xa00>;
reg = <0xfffff200 0x200
0xfffff400 0x200
0xfffff600 0x200
0xfffff800 0x200
0xfffffa00 0x200
>;
atmel,mux-mask = <
/* A B */
@@ -719,66 +713,65 @@
};
};
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
};
dbgu: serial@ffffee00 {

106
arch/arm/dts/at91sam9g45.dtsi
View File

@@ -435,12 +435,6 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff200 0xfffff200 0xa00>;
reg = <0xfffff200 0x200
0xfffff400 0x200
0xfffff600 0x200
0xfffff800 0x200
0xfffffa00 0x200
>;
bootph-all;
atmel,mux-mask = <
@@ -854,61 +848,61 @@
AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
};
};
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioDE_clk>;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioDE_clk>;
};
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioDE_clk>;
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioDE_clk>;
};
};
dbgu: serial@ffffee00 {

93
arch/arm/dts/at91sam9n12.dtsi
View File

@@ -492,11 +492,6 @@
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
reg = <0xfffff400 0x200
0xfffff600 0x200
0xfffff800 0x200
0xfffffa00 0x200
>;
atmel,mux-mask = <
/* A B C */
@@ -795,54 +790,54 @@
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
bootph-all;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
bootph-all;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
bootph-all;
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
bootph-all;
};
};
dbgu: serial@fffff200 {

93
arch/arm/dts/at91sam9rl.dtsi
View File

@@ -386,11 +386,6 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
reg = <0xfffff400 0x200
0xfffff600 0x200
0xfffff800 0x200
0xfffffa00 0x200
>;
atmel,mux-mask =
/* A B */
@@ -768,54 +763,54 @@
<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
bootph-all;
pioD: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
bootph-all;
};
};
pmc: pmc@fffffc00 {

90
arch/arm/dts/at91sam9x5.dtsi
View File

@@ -461,14 +461,8 @@
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
0xfffffa00 0x200 /* pioD */
>;
bootph-all;
/* shared pinctrl settings */
dbgu {
bootph-all;
@@ -831,52 +825,52 @@
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
};
ssc0: ssc@f0010000 {

11
arch/arm/dts/en7581-evb-u-boot.dtsi Normal file
View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/ {
/* When running as a first-stage bootloader this isn't filled in automatically */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x20000000>;
};
};
#include "an7581-u-boot.dtsi"

87
arch/arm/dts/imx6q-lxr.dts
View File

@@ -1,87 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Copyright 2024 Comvetia AG
/dts-v1/;
#include "imx6q-phytec-pfla02.dtsi"
/ {
model = "COMVETIA QSoIP LXR-2";
compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q";
chosen {
stdout-path = &uart4;
};
spi {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi_gpio>;
sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
#address-cells = <1>;
#size-cells = <0>;
fpga@0 {
compatible = "altr,fpga-passive-serial";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fpga>;
nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
};
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&fec {
status = "okay";
};
&i2c3 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&usdhc3 {
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_fpga: fpgagrp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
>;
};
pinctrl_spi_gpio: spigpiogrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0
MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0
>;
};
};

17
arch/arm/dts/imx6q-phytec-pfla02.dtsi
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@@ -1,17 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
*/
#include "imx6q.dtsi"
#include "imx6qdl-phytec-pfla02.dtsi"
/ {
model = "Phytec phyFLEX-i.MX6 Quad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
};
};

467
arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
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@@ -1,467 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
*/
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Phytec phyFLEX-i.MX6 Quad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 15 0>;
enable-active-high;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1_vbus>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 0 0>;
enable-active-high;
};
gpio_leds: leds {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
compatible = "gpio-leds";
led_green: led-green {
label = "phyflex:green";
gpios = <&gpio1 30 0>;
};
led_red: led-red {
label = "phyflex:red";
gpios = <&gpio2 31 0>;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "disabled";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "disabled";
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
som_flash: flash@0 {
compatible = "m25p80", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-handle = <&ethphy>;
phy-mode = "rgmii";
phy-reset-duration = <10>; /* in msecs */
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
phy-supply = <&vdd_eth_io_reg>;
status = "disabled";
fec_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
txc-skew-ps = <1680>;
rxc-skew-ps = <1860>;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
som_eeprom: eeprom@50 {
compatible = "catalyst,24c32", "atmel,24c32";
pagesize = <32>;
reg = <0x50>;
};
pmic@58 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
compatible = "dlg,da9063";
reg = <0x58>;
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
#interrupt-cells = <2>;
interrupt-controller;
regulators {
vddcore_reg: bcore1 {
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
regulator-always-on;
};
vddsoc_reg: bcore2 {
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
regulator-always-on;
};
vdd_ddr3_reg: bpro {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
vdd_3v3_reg: bperi {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_buckmem_reg: bmem {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_eth_reg: bio {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd_eth_io_reg: ldo4 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
vdd_mx6_snvs_reg: ldo5 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vdd_3v3_pmic_io_reg: ldo6 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_sd0_reg: ldo9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_sd1_reg: ldo10 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_mx6_high_reg: ldo11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
};
da9063_rtc: rtc {
compatible = "dlg,da9063-rtc";
};
da9063_wdog: watchdog {
compatible = "dlg,da9063-watchdog";
};
onkey {
compatible = "dlg,da9063-onkey";
status = "disabled";
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
};
&iomuxc {
imx6q-phytec-pfla02 {
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1_vbus: usbh1vbusgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_usdhc3_cdwp: usdhc3cdwp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
>;
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
status = "disabled";
};
&reg_arm {
vin-supply = <&vddcore_reg>;
};
&reg_pu {
vin-supply = <&vddsoc_reg>;
};
&reg_soc {
vin-supply = <&vddsoc_reg>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "disabled";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "disabled";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "disabled";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_sd1_reg>;
status = "disabled";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_sd0_reg>;
status = "disabled";
};
&wdog1 {
/*
* Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also
* used for reboot, does not reset all external PMIC voltages on reset.
*/
status = "disabled";
};

72
arch/arm/dts/imxrt1050-evk.dts
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@@ -1,72 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
/dts-v1/;
#include "imxrt1050.dtsi"
#include "imxrt1050-pinfunc.h"
/ {
model = "NXP IMXRT1050-evk board";
compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
chosen {
stdout-path = &lpuart1;
};
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
mmc0 = &usdhc1;
serial0 = &lpuart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x2000000>;
};
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
status = "okay";
};

993
arch/arm/dts/imxrt1050-pinfunc.h
View File

@@ -1,993 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
#define IMX_PAD_SION 0x40000000
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4
#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2
#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2
#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2
#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2
#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0
#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3
#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2
#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2
#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2
#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2
#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4
#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2
#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4
#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3
#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3
#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3
#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2
#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1
#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2
#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2
#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2
#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3
#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2
#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2
#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0
#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */

160
arch/arm/dts/imxrt1050.dtsi
View File

@@ -1,160 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include "armv7-m.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1050-clock.h>
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
clocks {
osc: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
osc3M: osc3M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
};
soc {
lpuart1: serial@40184000 {
compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x40184000 0x4000>;
interrupts = <20>;
clocks = <&clks IMXRT1050_CLK_LPUART1>;
clock-names = "ipg";
status = "disabled";
};
iomuxc: pinctrl@401f8000 {
compatible = "fsl,imxrt1050-iomuxc";
reg = <0x401f8000 0x4000>;
fsl,mux_mask = <0x7>;
};
anatop: anatop@400d8000 {
compatible = "fsl,imxrt-anatop";
reg = <0x400d8000 0x4000>;
};
clks: clock-controller@400fc000 {
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
interrupts = <95>, <96>;
clocks = <&osc>;
clock-names = "osc";
#clock-cells = <1>;
assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
<&clks IMXRT1050_CLK_PLL1_BYPASS>,
<&clks IMXRT1050_CLK_PLL2_BYPASS>,
<&clks IMXRT1050_CLK_PLL3_BYPASS>,
<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
<&clks IMXRT1050_CLK_PLL1_ARM>,
<&clks IMXRT1050_CLK_PLL2_SYS>,
<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
<&clks IMXRT1050_CLK_PLL2_SYS>;
};
edma1: dma-controller@400e8000 {
#dma-cells = <2>;
compatible = "fsl,imx7ulp-edma";
reg = <0x400e8000 0x4000>,
<0x400ec000 0x4000>;
dma-channels = <32>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
<9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
clock-names = "dma", "dmamux0";
clocks = <&clks IMXRT1050_CLK_DMA>,
<&clks IMXRT1050_CLK_DMA_MUX>;
};
usdhc1: mmc@402c0000 {
compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
reg = <0x402c0000 0x4000>;
interrupts = <110>;
clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
<&clks IMXRT1050_CLK_AHB_PODF>,
<&clks IMXRT1050_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,wp-controller;
no-1-8-v;
max-frequency = <4000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
status = "disabled";
};
gpio1: gpio@401b8000 {
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <80>, <81>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@401bc000 {
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <82>, <83>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@401c0000 {
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <84>, <85>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@401c4000 {
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401c4000 0x4000>;
interrupts = <86>, <87>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@400c0000 {
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <88>, <89>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpt: timer@401ec000 {
compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
reg = <0x401ec000 0x4000>;
interrupts = <100>;
clocks = <&osc3M>;
clock-names = "per";
};
};
};

25
arch/arm/dts/ipq9574-rdp433-u-boot.dtsi Normal file
View File

@@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/ {
/* Will be removed when SMEM parsing is updated */
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x40000000>,
<0x0 0x4a500000 0x0 0x00100000>;
};
};
&sdhc_1 {
sdhci-caps-mask = <0x0 0x04000000>;
sdhci-caps = <0x0 0x04000000>; /* SDHCI_CAN_VDD_180 */
/*
* This reset is needed to clear out the settings done by
* previous boot loader. Without this the SDHCI_RESET_ALL
* reset done sdhci_init() times out.
*/
resets = <&gcc GCC_SDCC_BCR>;
};

16
arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07
* Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time)
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb
@@ -13,6 +13,8 @@
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 16
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -847,7 +849,7 @@
#define DDRSS_PHY_62_DATA 0x00000000
#define DDRSS_PHY_63_DATA 0x00000000
#define DDRSS_PHY_64_DATA 0x00000000
#define DDRSS_PHY_65_DATA 0x00000004
#define DDRSS_PHY_65_DATA 0x00000104
#define DDRSS_PHY_66_DATA 0x00000000
#define DDRSS_PHY_67_DATA 0x00000000
#define DDRSS_PHY_68_DATA 0x00000000
@@ -869,7 +871,7 @@
#define DDRSS_PHY_84_DATA 0x00100010
#define DDRSS_PHY_85_DATA 0x00100010
#define DDRSS_PHY_86_DATA 0x00100010
#define DDRSS_PHY_87_DATA 0x02020010
#define DDRSS_PHY_87_DATA 0x02000010
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
#define DDRSS_PHY_90_DATA 0x07AB0340
@@ -1103,7 +1105,7 @@
#define DDRSS_PHY_318_DATA 0x00000000
#define DDRSS_PHY_319_DATA 0x00000000
#define DDRSS_PHY_320_DATA 0x00000000
#define DDRSS_PHY_321_DATA 0x00000004
#define DDRSS_PHY_321_DATA 0x00000104
#define DDRSS_PHY_322_DATA 0x00000000
#define DDRSS_PHY_323_DATA 0x00000000
#define DDRSS_PHY_324_DATA 0x00000000
@@ -1125,7 +1127,7 @@
#define DDRSS_PHY_340_DATA 0x00100010
#define DDRSS_PHY_341_DATA 0x00100010
#define DDRSS_PHY_342_DATA 0x00100010
#define DDRSS_PHY_343_DATA 0x02020010
#define DDRSS_PHY_343_DATA 0x02000010
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
#define DDRSS_PHY_346_DATA 0x07AB0340
@@ -2181,7 +2183,7 @@
#define DDRSS_PHY_1396_DATA 0x0089FF00
#define DDRSS_PHY_1397_DATA 0x000C3F11
#define DDRSS_PHY_1398_DATA 0x01990000
#define DDRSS_PHY_1399_DATA 0x000C3F11
#define DDRSS_PHY_1399_DATA 0x000C3F91
#define DDRSS_PHY_1400_DATA 0x01990000
#define DDRSS_PHY_1401_DATA 0x3F0DFF11
#define DDRSS_PHY_1402_DATA 0x01990000

4
arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
View File

@@ -177,6 +177,10 @@
bootph-all;
};
&usb0_phy_ctrl {
bootph-all;
};
&vcc_3v3_mmc {
bootph-all;
};

50
arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01
* Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time)
* AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 10:55:17 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 1866MHz
* Density (per channel): 8Gb
@@ -12,6 +12,8 @@
#define DDRSS_PLL_FHS_CNT 5
#define DDRSS_PLL_FREQUENCY_1 933000000
#define DDRSS_PLL_FREQUENCY_2 933000000
#define DDRSS_SDRAM_IDX 16
#define DDRSS_REGION_IDX 17
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -402,10 +404,10 @@
#define DDRSS_CTL_386_DATA 0x01090903
#define DDRSS_CTL_387_DATA 0x05020201
#define DDRSS_CTL_388_DATA 0x0E081B1B
#define DDRSS_CTL_389_DATA 0x0008030E
#define DDRSS_CTL_390_DATA 0x0B12030E
#define DDRSS_CTL_391_DATA 0x0B120314
#define DDRSS_CTL_392_DATA 0x12120814
#define DDRSS_CTL_389_DATA 0x0008040E
#define DDRSS_CTL_390_DATA 0x0B120406
#define DDRSS_CTL_391_DATA 0x0B120406
#define DDRSS_CTL_392_DATA 0x12120806
#define DDRSS_CTL_393_DATA 0x01000000
#define DDRSS_CTL_394_DATA 0x07030701
#define DDRSS_CTL_395_DATA 0x04000103
@@ -417,8 +419,8 @@
#define DDRSS_CTL_401_DATA 0x00000200
#define DDRSS_CTL_402_DATA 0x00000693
#define DDRSS_CTL_403_DATA 0x00000E9C
#define DDRSS_CTL_404_DATA 0x03050202
#define DDRSS_CTL_405_DATA 0x37200201
#define DDRSS_CTL_404_DATA 0x03000202
#define DDRSS_CTL_405_DATA 0x37200404
#define DDRSS_CTL_406_DATA 0x000038C8
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x00000200
@@ -426,8 +428,8 @@
#define DDRSS_CTL_410_DATA 0x00000200
#define DDRSS_CTL_411_DATA 0x0000FF84
#define DDRSS_CTL_412_DATA 0x000237D0
#define DDRSS_CTL_413_DATA 0x111F0402
#define DDRSS_CTL_414_DATA 0x37200C0D
#define DDRSS_CTL_413_DATA 0x111A0402
#define DDRSS_CTL_414_DATA 0x37200C09
#define DDRSS_CTL_415_DATA 0x000038C8
#define DDRSS_CTL_416_DATA 0x00000200
#define DDRSS_CTL_417_DATA 0x00000200
@@ -435,8 +437,8 @@
#define DDRSS_CTL_419_DATA 0x00000200
#define DDRSS_CTL_420_DATA 0x0000FF84
#define DDRSS_CTL_421_DATA 0x000237D0
#define DDRSS_CTL_422_DATA 0x111F0402
#define DDRSS_CTL_423_DATA 0x00200C0D
#define DDRSS_CTL_422_DATA 0x111A0402
#define DDRSS_CTL_423_DATA 0x00200C09
#define DDRSS_CTL_424_DATA 0x00000000
#define DDRSS_CTL_425_DATA 0x02000A00
#define DDRSS_CTL_426_DATA 0x00050003
@@ -939,7 +941,7 @@
#define DDRSS_PHY_64_DATA 0x00000000
#define DDRSS_PHY_65_DATA 0x00000000
#define DDRSS_PHY_66_DATA 0x00000000
#define DDRSS_PHY_67_DATA 0x00000004
#define DDRSS_PHY_67_DATA 0x00000104
#define DDRSS_PHY_68_DATA 0x00000000
#define DDRSS_PHY_69_DATA 0x00000000
#define DDRSS_PHY_70_DATA 0x00000000
@@ -964,7 +966,7 @@
#define DDRSS_PHY_89_DATA 0x00100010
#define DDRSS_PHY_90_DATA 0x00100010
#define DDRSS_PHY_91_DATA 0x00100010
#define DDRSS_PHY_92_DATA 0x02040010
#define DDRSS_PHY_92_DATA 0x02000010
#define DDRSS_PHY_93_DATA 0x00000005
#define DDRSS_PHY_94_DATA 0x51516042
#define DDRSS_PHY_95_DATA 0x31C06000
@@ -1195,7 +1197,7 @@
#define DDRSS_PHY_320_DATA 0x00000000
#define DDRSS_PHY_321_DATA 0x00000000
#define DDRSS_PHY_322_DATA 0x00000000
#define DDRSS_PHY_323_DATA 0x00000004
#define DDRSS_PHY_323_DATA 0x00000104
#define DDRSS_PHY_324_DATA 0x00000000
#define DDRSS_PHY_325_DATA 0x00000000
#define DDRSS_PHY_326_DATA 0x00000000
@@ -1220,7 +1222,7 @@
#define DDRSS_PHY_345_DATA 0x00100010
#define DDRSS_PHY_346_DATA 0x00100010
#define DDRSS_PHY_347_DATA 0x00100010
#define DDRSS_PHY_348_DATA 0x02040010
#define DDRSS_PHY_348_DATA 0x02000010
#define DDRSS_PHY_349_DATA 0x00000005
#define DDRSS_PHY_350_DATA 0x51516042
#define DDRSS_PHY_351_DATA 0x31C06000
@@ -1451,7 +1453,7 @@
#define DDRSS_PHY_576_DATA 0x00000000
#define DDRSS_PHY_577_DATA 0x00000000
#define DDRSS_PHY_578_DATA 0x00000000
#define DDRSS_PHY_579_DATA 0x00000004
#define DDRSS_PHY_579_DATA 0x00000104
#define DDRSS_PHY_580_DATA 0x00000000
#define DDRSS_PHY_581_DATA 0x00000000
#define DDRSS_PHY_582_DATA 0x00000000
@@ -1476,7 +1478,7 @@
#define DDRSS_PHY_601_DATA 0x00100010
#define DDRSS_PHY_602_DATA 0x00100010
#define DDRSS_PHY_603_DATA 0x00100010
#define DDRSS_PHY_604_DATA 0x02040010
#define DDRSS_PHY_604_DATA 0x02000010
#define DDRSS_PHY_605_DATA 0x00000005
#define DDRSS_PHY_606_DATA 0x51516042
#define DDRSS_PHY_607_DATA 0x31C06000
@@ -1707,7 +1709,7 @@
#define DDRSS_PHY_832_DATA 0x00000000
#define DDRSS_PHY_833_DATA 0x00000000
#define DDRSS_PHY_834_DATA 0x00000000
#define DDRSS_PHY_835_DATA 0x00000004
#define DDRSS_PHY_835_DATA 0x00000104
#define DDRSS_PHY_836_DATA 0x00000000
#define DDRSS_PHY_837_DATA 0x00000000
#define DDRSS_PHY_838_DATA 0x00000000
@@ -1732,7 +1734,7 @@
#define DDRSS_PHY_857_DATA 0x00100010
#define DDRSS_PHY_858_DATA 0x00100010
#define DDRSS_PHY_859_DATA 0x00100010
#define DDRSS_PHY_860_DATA 0x02040010
#define DDRSS_PHY_860_DATA 0x02000010
#define DDRSS_PHY_861_DATA 0x00000005
#define DDRSS_PHY_862_DATA 0x51516042
#define DDRSS_PHY_863_DATA 0x31C06000
@@ -2699,7 +2701,7 @@
#define DDRSS_PHY_1824_DATA 0x0F0F0804
#define DDRSS_PHY_1825_DATA 0x00800120
#define DDRSS_PHY_1826_DATA 0x00041B42
#define DDRSS_PHY_1827_DATA 0x00005201
#define DDRSS_PHY_1827_DATA 0x00004201
#define DDRSS_PHY_1828_DATA 0x00000000
#define DDRSS_PHY_1829_DATA 0x00000000
#define DDRSS_PHY_1830_DATA 0x00000000
@@ -2760,7 +2762,7 @@
#define DDRSS_PHY_1885_DATA 0x00000002
#define DDRSS_PHY_1886_DATA 0x00000000
#define DDRSS_PHY_1887_DATA 0x00000000
#define DDRSS_PHY_1888_DATA 0x00000AC4
#define DDRSS_PHY_1888_DATA 0x0001F7C4
#define DDRSS_PHY_1889_DATA 0x04000004
#define DDRSS_PHY_1890_DATA 0x00000000
#define DDRSS_PHY_1891_DATA 0x00001142
@@ -2789,10 +2791,10 @@
#define DDRSS_PHY_1914_DATA 0x0089FF00
#define DDRSS_PHY_1915_DATA 0x000C3F11
#define DDRSS_PHY_1916_DATA 0x01990000
#define DDRSS_PHY_1917_DATA 0x000C3F11
#define DDRSS_PHY_1917_DATA 0x000C3F91
#define DDRSS_PHY_1918_DATA 0x01990000
#define DDRSS_PHY_1919_DATA 0x3F0DFF11
#define DDRSS_PHY_1920_DATA 0x00EF0000
#define DDRSS_PHY_1921_DATA 0x00018011
#define DDRSS_PHY_1922_DATA 0x0089FF00
#define DDRSS_PHY_1923_DATA 0x20040004
#define DDRSS_PHY_1923_DATA 0x20040006

109
arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
View File

@@ -142,7 +142,21 @@
};
};
};
#endif
#include "k3-binman-capsule-r5.dtsi"
&capsule_tiboot3 {
efi-capsule {
/*
* The GUID is generated dynamically by taking a namespace UUID and hashing
* it with the board compatible and fw_image name:
* mkeficapsule guidgen k3-am62a7-r5-phycore-som-2gb.dtb PHYCORE_AM62AX_TIBOOT3
*/
image-guid = "07CA7DD0-85FF-597E-A485-B2423D3AE6C1";
};
};
#endif /* CONFIG_TARGET_PHYCORE_AM62AX_R5 */
#ifdef CONFIG_TARGET_PHYCORE_AM62AX_A53
@@ -306,6 +320,66 @@
description = "U-Boot for AM62Ax board";
};
som-no-rtc {
description = "k3-am6xx-phycore-disable-rtc";
type = "flat_dt";
compression = "none";
load = <0x8F000000>;
arch = "arm";
ti-secure {
content = <&am6xx_phycore_disable_rtc_dtbo>;
keyfile = "custMpk.pem";
};
am6xx_phycore_disable_rtc_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
};
};
som-no-spi {
description = "k3-am6xx-phycore-disable-spi-nor";
type = "flat_dt";
compression = "none";
load = <0x8F001000>;
arch = "arm";
ti-secure {
content = <&am6xx_phycore_disable_spi_not_dtbo>;
keyfile = "custMpk.pem";
};
am6xx_phycore_disable_spi_not_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
};
};
som-no-eth {
description = "k3-am6xx-phycore-disable-eth-phy";
type = "flat_dt";
compression = "none";
load = <0x8F002000>;
arch = "arm";
ti-secure {
content = <&am6xx_phycore_disable_eth_phy_dtbo>;
keyfile = "custMpk.pem";
};
am6xx_phycore_disable_eth_phy_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
};
};
som-qspi {
description = "k3-am6xx-phycore-qspi-nor";
type = "flat_dt";
compression = "none";
load = <0x8F003000>;
arch = "arm";
ti-secure {
content = <&am6xx_phycore_disable_qspi_nor_dtbo>;
keyfile = "custMpk.pem";
};
am6xx_phycore_disable_qspi_nor_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
};
};
fdt-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
type = "flat_dt";
@@ -330,7 +404,11 @@
conf-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "uboot";
loadables = "uboot";
loadables = "uboot",
"som-no-rtc",
"som-no-spi",
"som-no-eth",
"som-qspi";
fdt = "fdt-0";
};
};
@@ -451,4 +529,29 @@
};
};
};
#endif
#include "k3-binman-capsule.dtsi"
&capsule_tispl {
efi-capsule {
/*
* The GUID is generated dynamically by taking a namespace UUID and hashing
* it with the board compatible and fw_image name:
* mkeficapsule guidgen k3-am62a7-phyboard-lyra-rdk.dtb PHYCORE_AM62AX_SPL
*/
image-guid = "14F968A2-7C3A-50AD-9356-192F07AD2A9C";
};
};
&capsule_uboot {
efi-capsule {
/*
* The GUID is generated dynamically by taking a namespace UUID and hashing
* it with the board compatible and fw_image name:
* mkeficapsule guidgen k3-am62a7-phyboard-lyra-rdk.dtb PHYCORE_AM62AX_UBOOT
*/
image-guid = "1F1148C5-2785-5E7C-9C58-C5B1EC0DC80C";
};
};
#endif /* CONFIG_TARGET_PHYCORE_AM62AX_A53 */

4
arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
View File

@@ -239,6 +239,10 @@
bootph-all;
};
&usb0_phy_ctrl {
bootph-all;
};
&vcc_3v3_mmc {
bootph-all;
};

104
arch/arm/dts/k3-am62a7.dtsi
View File

@@ -1,104 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A7 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/zip/spruj16
*
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am62a.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x002>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x003>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};

12
arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02
* Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time)
* AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 1600MHz
* Density (per channel): 16Gb
@@ -941,7 +941,7 @@
#define DDRSS_PHY_64_DATA 0x00000000
#define DDRSS_PHY_65_DATA 0x00000000
#define DDRSS_PHY_66_DATA 0x00000000
#define DDRSS_PHY_67_DATA 0x00000004
#define DDRSS_PHY_67_DATA 0x00000104
#define DDRSS_PHY_68_DATA 0x00000000
#define DDRSS_PHY_69_DATA 0x00000000
#define DDRSS_PHY_70_DATA 0x00000000
@@ -1197,7 +1197,7 @@
#define DDRSS_PHY_320_DATA 0x00000000
#define DDRSS_PHY_321_DATA 0x00000000
#define DDRSS_PHY_322_DATA 0x00000000
#define DDRSS_PHY_323_DATA 0x00000004
#define DDRSS_PHY_323_DATA 0x00000104
#define DDRSS_PHY_324_DATA 0x00000000
#define DDRSS_PHY_325_DATA 0x00000000
#define DDRSS_PHY_326_DATA 0x00000000
@@ -1453,7 +1453,7 @@
#define DDRSS_PHY_576_DATA 0x00000000
#define DDRSS_PHY_577_DATA 0x00000000
#define DDRSS_PHY_578_DATA 0x00000000
#define DDRSS_PHY_579_DATA 0x00000004
#define DDRSS_PHY_579_DATA 0x00000104
#define DDRSS_PHY_580_DATA 0x00000000
#define DDRSS_PHY_581_DATA 0x00000000
#define DDRSS_PHY_582_DATA 0x00000000
@@ -1709,7 +1709,7 @@
#define DDRSS_PHY_832_DATA 0x00000000
#define DDRSS_PHY_833_DATA 0x00000000
#define DDRSS_PHY_834_DATA 0x00000000
#define DDRSS_PHY_835_DATA 0x00000004
#define DDRSS_PHY_835_DATA 0x00000104
#define DDRSS_PHY_836_DATA 0x00000000
#define DDRSS_PHY_837_DATA 0x00000000
#define DDRSS_PHY_838_DATA 0x00000000

14
arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60
* Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time)
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:00:17 GMT+0530 (India Standard Time)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
@@ -12,6 +12,8 @@
#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 17
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -334,7 +336,7 @@
#define DDRSS_CTL_318_DATA 0x3FFF0000
#define DDRSS_CTL_319_DATA 0x000FFF00
#define DDRSS_CTL_320_DATA 0xFFFFFFFF
#define DDRSS_CTL_321_DATA 0x000FFF00
#define DDRSS_CTL_321_DATA 0x00FFFF00
#define DDRSS_CTL_322_DATA 0x0A000000
#define DDRSS_CTL_323_DATA 0x0001FFFF
#define DDRSS_CTL_324_DATA 0x01010101
@@ -901,7 +903,7 @@
#define DDRSS_PHY_117_DATA 0x00800080
#define DDRSS_PHY_118_DATA 0x00800080
#define DDRSS_PHY_119_DATA 0x01000080
#define DDRSS_PHY_120_DATA 0x01A00000
#define DDRSS_PHY_120_DATA 0x01000000
#define DDRSS_PHY_121_DATA 0x00000000
#define DDRSS_PHY_122_DATA 0x00000000
#define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1159,7 @@
#define DDRSS_PHY_373_DATA 0x00800080
#define DDRSS_PHY_374_DATA 0x00800080
#define DDRSS_PHY_375_DATA 0x01000080
#define DDRSS_PHY_376_DATA 0x01A00000
#define DDRSS_PHY_376_DATA 0x01000000
#define DDRSS_PHY_377_DATA 0x00000000
#define DDRSS_PHY_378_DATA 0x00000000
#define DDRSS_PHY_379_DATA 0x00080200
@@ -2152,7 +2154,7 @@
#define DDRSS_PHY_1368_DATA 0x00000002
#define DDRSS_PHY_1369_DATA 0x00000100
#define DDRSS_PHY_1370_DATA 0x00000000
#define DDRSS_PHY_1371_DATA 0x0001F7C0
#define DDRSS_PHY_1371_DATA 0x0001F7C2
#define DDRSS_PHY_1372_DATA 0x00020002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142

16
arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
* Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time)
* AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
@@ -12,6 +12,8 @@
#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 15
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -178,7 +180,7 @@
#define DDRSS_CTL_162_DATA 0x0E0A0907
#define DDRSS_CTL_163_DATA 0x0A090000
#define DDRSS_CTL_164_DATA 0x0A090701
#define DDRSS_CTL_165_DATA 0x0000000E
#define DDRSS_CTL_165_DATA 0x0000080E
#define DDRSS_CTL_166_DATA 0x00040003
#define DDRSS_CTL_167_DATA 0x00000007
#define DDRSS_CTL_168_DATA 0x00000000
@@ -334,7 +336,7 @@
#define DDRSS_CTL_318_DATA 0x3FFF0000
#define DDRSS_CTL_319_DATA 0x000FFF00
#define DDRSS_CTL_320_DATA 0xFFFFFFFF
#define DDRSS_CTL_321_DATA 0x000FFF00
#define DDRSS_CTL_321_DATA 0x00FFFF00
#define DDRSS_CTL_322_DATA 0x0A000000
#define DDRSS_CTL_323_DATA 0x0001FFFF
#define DDRSS_CTL_324_DATA 0x01010101
@@ -901,7 +903,7 @@
#define DDRSS_PHY_117_DATA 0x00800080
#define DDRSS_PHY_118_DATA 0x00800080
#define DDRSS_PHY_119_DATA 0x01000080
#define DDRSS_PHY_120_DATA 0x01A00000
#define DDRSS_PHY_120_DATA 0x01000000
#define DDRSS_PHY_121_DATA 0x00000000
#define DDRSS_PHY_122_DATA 0x00000000
#define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1159,7 @@
#define DDRSS_PHY_373_DATA 0x00800080
#define DDRSS_PHY_374_DATA 0x00800080
#define DDRSS_PHY_375_DATA 0x01000080
#define DDRSS_PHY_376_DATA 0x01A00000
#define DDRSS_PHY_376_DATA 0x01000000
#define DDRSS_PHY_377_DATA 0x00000000
#define DDRSS_PHY_378_DATA 0x00000000
#define DDRSS_PHY_379_DATA 0x00080200
@@ -2152,7 +2154,7 @@
#define DDRSS_PHY_1368_DATA 0x00000002
#define DDRSS_PHY_1369_DATA 0x00000100
#define DDRSS_PHY_1370_DATA 0x00000000
#define DDRSS_PHY_1371_DATA 0x0001F7C0
#define DDRSS_PHY_1371_DATA 0x0001F7C2
#define DDRSS_PHY_1372_DATA 0x00020002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142

18
arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
View File

@@ -14,6 +14,24 @@
spi0 = &ospi0;
};
sysinfo {
compatible = "siemens,sysinfo-iot2050";
/* TI_SRAM_SCRATCH_BOARD_EEPROM_START */
offset = <0x40280000>;
bootph-all;
smbios {
system {
manufacturer = "SIEMENS AG";
product = "SIMATIC IOT2050";
};
baseboard {
manufacturer = "SIEMENS AG";
};
};
};
leds {
bootph-all;
status-led-red {

270
arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi Normal file
View File

@@ -0,0 +1,270 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common AM67A BeagleY-AI dts file for SPLs
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
};
&main_pktdma {
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x20000>,
<0x00 0x484a0000 0x00 0x4000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan", "rflow";
};
&dmsc {
bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
};
};
&usbss0 {
bootph-pre-ram;
};
&usb0 {
dr_mode = "peripheral";
bootph-pre-ram;
};
&usbss1 {
status = "disabled";
};
&usb1 {
status = "disabled";
};
#if IS_ENABLED(CONFIG_TARGET_J722S_R5_BEAGLEY_AI)
&binman {
tiboot3-j722s-hs-evm.bin {
filename = "tiboot3-j722s-hs-evm.bin";
ti-secure-rom {
content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
<&combined_dm_cfg>, <&sysfw_inner_cert>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl>;
content-sysfw = <&ti_fs_enc>;
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <0x43c00000>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c7a800>;
};
u_boot_spl: u-boot-spl {
no-expanded;
};
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
&binman {
tiboot3-j722s-hs-fs-evm.bin {
filename = "tiboot3-j722s-hs-fs-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl_fs>;
content-sysfw = <&ti_fs_enc_fs>;
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c7a800>;
};
u_boot_spl_fs: u-boot-spl {
no-expanded;
};
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
#endif /* CONFIG_TARGET_J722S_R5_BEAGLEY_AI */
#if IS_ENABLED(CONFIG_TARGET_J722S_A53_BEAGLEY_AI)
#define SPL_BEAGLEY_AI_DTB "spl/dts/ti/k3-am67a-beagley-ai.dtb"
#define BEAGLEY_AI_DTB "u-boot.dtb"
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
dm {
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: ti-dm {
filename = "ti-dm.bin";
};
};
fdt-0 {
description = "k3-am67a-beagley-ai";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_beagley_ai_dtb>;
keyfile = "custMpk.pem";
};
spl_beagley_ai_dtb: blob-ext {
filename = "spl/dts/ti/k3-am67a-beagley-ai.dtb";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am67a-beagley-ai";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for BeagleY-AI";
};
fdt-0 {
description = "k3-am67a-beagley-ai";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&beagley_ai_dtb>;
keyfile = "custMpk.pem";
};
beagley_ai_dtb: blob-ext {
filename = "u-boot.dtb";
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-k3-am67a-beagley-ai";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif /* CONFIG_TARGET_J722S_A53_BEAGLEY_AI */

2801
arch/arm/dts/k3-am67a-beagley-ddr-lp4.dtsi Normal file
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File diff suppressed because it is too large Load Diff

84
arch/arm/dts/k3-am67a-r5-beagley-ai.dts Normal file
View File

@@ -0,0 +1,84 @@
// SPDX-License-Identifier: GPL-2.0
/*
* AM67A BeagleY-AI dts file for R5 SPL
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-am67a-beagley-ai.dts"
#include "k3-am67a-beagley-ai-u-boot.dtsi"
#include "k3-am67a-beagley-ddr-lp4.dtsi"
#include "k3-am62a-ddr.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
};

123
arch/arm/dts/k3-am69-sk-u-boot.dtsi
View File

@@ -1,10 +1,109 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#define SPL_BOARD_DTB "spl/dts/ti/k3-am69-sk.dtb"
#define BOARD_DESCRIPTION "k3-am69-sk"
#define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 board"
#include "k3-j784s4-binman.dtsi"
#if defined(CONFIG_CPU_V7R)
&binman {
tiboot3-am69-hs {
insert-template = <&tiboot3_j784s4_hs>;
filename = "tiboot3-j784s4-hs-evm.bin";
};
tiboot3-am69-hs-fs {
insert-template = <&tiboot3_j784s4_hs_fs>;
filename = "tiboot3-j784s4-hs-fs-evm.bin";
symlink = "tiboot3.bin";
};
};
&ti_fs_enc {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
};
&sysfw_inner_cert {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
};
&ti_fs_enc_fs {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
};
&sysfw_inner_cert_fs {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
};
#include "k3-binman-capsule-r5.dtsi"
// Capsule update GUIDs in string form. See j784s4_evm.h
#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46"
&capsule_tiboot3 {
efi-capsule {
image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR;
blob {
filename = "tiboot3-j784s4-hs-fs-evm.bin";
};
};
};
#else // CONFIG_ARM64
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
tispl {
insert-template = <&ti_spl>;
};
u-boot {
insert-template = <&u_boot>;
};
tispl-unsigned {
insert-template = <&ti_spl_unsigned>;
};
u-boot-unsigned {
insert-template = <&u_boot_unsigned>;
};
};
#include "k3-binman-capsule.dtsi"
// Capsule update GUIDs in string form. See j784s4_evm.h
#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e"
#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617"
&capsule_tispl {
efi-capsule {
image-guid = AM69_SK_SPL_IMAGE_GUID_STR;
};
};
&capsule_uboot {
efi-capsule {
image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR;
};
};
#endif
/ {
memory@80000000 {
bootph-all;
@@ -23,25 +122,3 @@
bootph-pre-ram;
};
#ifdef CONFIG_TARGET_J784S4_A72_EVM
#define SPL_AM69_SK_DTB "spl/dts/ti/k3-am69-sk.dtb"
#define AM69_SK_DTB "u-boot.dtb"
&spl_j784s4_evm_dtb {
filename = SPL_AM69_SK_DTB;
};
&j784s4_evm_dtb {
filename = AM69_SK_DTB;
};
&spl_j784s4_evm_dtb_unsigned {
filename = SPL_AM69_SK_DTB;
};
&j784s4_evm_dtb_unsigned {
filename = AM69_SK_DTB;
};
#endif

40
arch/arm/dts/k3-j7200-binman.dtsi
View File

@@ -7,46 +7,6 @@
#ifdef CONFIG_TARGET_J7200_R5_EVM
&bcfg_yaml {
config = "board-cfg_j7200.yaml";
};
&rcfg_yaml {
config = "rm-cfg_j7200.yaml";
};
&pcfg_yaml {
config = "pm-cfg_j7200.yaml";
};
&scfg_yaml {
config = "sec-cfg_j7200.yaml";
};
&bcfg_yaml_tifs {
config = "board-cfg_j7200.yaml";
};
&rcfg_yaml_tifs {
config = "rm-cfg_j7200.yaml";
};
&pcfg_yaml_tifs {
config = "pm-cfg_j7200.yaml";
};
&scfg_yaml_tifs {
config = "sec-cfg_j7200.yaml";
};
&rcfg_yaml_dm {
config = "rm-cfg_j7200.yaml";
};
&pcfg_yaml_dm {
config = "pm-cfg_j7200.yaml";
};
&binman {
tiboot3-j7200-hs-evm.bin {
filename = "tiboot3-j7200-hs-evm.bin";

7
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
View File

@@ -120,3 +120,10 @@
vdd-supply-2 = <&buckb1>;
bootph-pre-ram;
};
&tps659414 {
esm: esm {
compatible = "ti,tps659413-esm";
bootph-pre-ram;
};
};

8756
arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi Normal file
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File diff suppressed because it is too large Load Diff

72
arch/arm/dts/k3-j742s2-evm-u-boot.dtsi Normal file
View File

@@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#define SPL_BOARD_DTB "spl/dts/ti/k3-j742s2-evm.dtb"
#define BOARD_DESCRIPTION "k3-j742s2-evm"
#define UBOOT_BOARD_DESCRIPTION "U-Boot for J742S2 board"
#include "k3-j784s4-binman.dtsi"
#if !defined(CONFIG_ARM64)
&binman {
tiboot3-j742s2-hs-fs {
insert-template = <&tiboot3_j784s4_hs_fs>;
filename = "tiboot3-j742s2-hs-fs-evm.bin";
symlink = "tiboot3.bin";
};
tiboot3-j742s2-hs {
insert-template = <&tiboot3_j784s4_hs>;
filename = "tiboot3-j742s2-hs-evm.bin";
};
};
&ti_fs_enc_fs {
filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-fs-enc.bin";
};
&sysfw_inner_cert_fs {
filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-fs-cert.bin";
};
&ti_fs_enc {
filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-enc.bin";
};
&sysfw_inner_cert {
filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-cert.bin";
};
#else // CONFIG_ARM64
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
tispl {
insert-template = <&ti_spl>;
};
u-boot {
insert-template = <&u_boot>;
};
tispl-unsigned {
insert-template = <&ti_spl_unsigned>;
};
u-boot-unsigned {
insert-template = <&u_boot_unsigned>;
};
};
#endif

18
arch/arm/dts/k3-j742s2-r5-evm.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j742s2-evm.dts"
#include "k3-j742s2-ddr-evm-lp4-4266.dtsi"
#include "k3-j784s4-j742s2-ddr.dtsi"
#include "k3-j742s2-evm-u-boot.dtsi"
#include "k3-j784s4-r5.dtsi"
&tps659413 {
esm: esm {
compatible = "ti,tps659413-esm";
bootph-pre-ram;
};
};

116
arch/arm/dts/k3-j784s4-binman.dtsi
View File

@@ -5,16 +5,15 @@
#include "k3-binman.dtsi"
#ifdef CONFIG_TARGET_J784S4_R5_EVM
#if defined(CONFIG_CPU_V7R)
&rcfg_yaml_tifs {
config = "tifs-rm-cfg.yaml";
};
&binman {
tiboot3-j784s4-hs-evm.bin {
filename = "tiboot3-j784s4-hs-evm.bin";
tiboot3_j784s4_hs: template-9 {
section {
ti-secure-rom {
content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
<&combined_dm_cfg>, <&sysfw_inner_cert>;
@@ -39,7 +38,6 @@
};
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
type = "blob-ext";
optional;
};
@@ -50,7 +48,6 @@
};
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
type = "blob-ext";
optional;
};
@@ -59,13 +56,13 @@
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
};
&binman {
tiboot3-j784s4-hs-fs-evm.bin {
filename = "tiboot3-j784s4-hs-fs-evm.bin";
tiboot3_j784s4_hs_fs: template-10 {
section {
ti-secure-rom {
content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
@@ -90,7 +87,6 @@
};
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
@@ -101,7 +97,6 @@
};
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
@@ -110,14 +105,13 @@
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
};
&binman {
tiboot3-j784s4-gp-evm.bin {
filename = "tiboot3-j784s4-gp-evm.bin";
symlink = "tiboot3.bin";
tiboot3_j784s4_gp: template-11 {
section {
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
@@ -140,7 +134,6 @@
};
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
type = "blob-ext";
optional;
};
@@ -154,43 +147,14 @@
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
#include "k3-binman-capsule-r5.dtsi"
// Capsule update GUIDs in string form. See j784s4_evm.h
#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46"
&capsule_tiboot3 {
efi-capsule {
image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR;
blob {
filename = "tiboot3-j784s4-hs-fs-evm.bin";
};
};
};
#endif
#ifdef CONFIG_TARGET_J784S4_A72_EVM
#define SPL_J784S4_EVM_DTB "spl/dts/ti/k3-j784s4-evm.dtb"
#define J784S4_EVM_DTB "u-boot.dtb"
#else
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
ti-spl {
ti_spl: template-12 {
insert-template = <&ti_spl_template>;
fit {
@@ -207,19 +171,20 @@
};
fdt-0 {
description = "k3-j784s4-evm";
description = BOARD_DESCRIPTION;
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_j784s4_evm_dtb>;
content = <&spl_board_dtb>;
keyfile = "custMpk.pem";
};
spl_j784s4_evm_dtb: blob-ext {
filename = SPL_J784S4_EVM_DTB;
spl_board_dtb: blob-ext {
filename = SPL_BOARD_DTB;
};
};
};
@@ -227,7 +192,7 @@
default = "conf-0";
conf-0 {
description = "k3-j784s4-evm";
description = BOARD_DESCRIPTION;
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
@@ -238,17 +203,17 @@
};
&binman {
u-boot {
u_boot: template-13 {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for J784S4 board";
description = UBOOT_BOARD_DESCRIPTION;
};
fdt-0 {
description = "k3-j784s4-evm";
description = BOARD_DESCRIPTION;
type = "flat_dt";
arch = "arm";
compression = "none";
@@ -259,7 +224,7 @@
};
j784s4_evm_dtb: blob-ext {
filename = J784S4_EVM_DTB;
filename = "u-boot.dtb";
};
hash {
@@ -272,7 +237,7 @@
default = "conf-0";
conf-0 {
description = "k3-j784s4-evm";
description = BOARD_DESCRIPTION;
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
@@ -283,7 +248,7 @@
};
&binman {
ti-spl_unsigned {
ti_spl_unsigned: template-14 {
insert-template = <&ti_spl_unsigned_template>;
fit {
@@ -295,13 +260,13 @@
};
fdt-0 {
description = "k3-j784s4-evm";
description = BOARD_DESCRIPTION;
type = "flat_dt";
arch = "arm";
compression = "none";
spl_j784s4_evm_dtb_unsigned: blob {
filename = SPL_J784S4_EVM_DTB;
filename = SPL_BOARD_DTB;
};
};
};
@@ -310,7 +275,7 @@
default = "conf-0";
conf-0 {
description = "k3-j784s4-evm";
description = BOARD_DESCRIPTION;
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
@@ -321,23 +286,23 @@
};
&binman {
u-boot_unsigned {
u_boot_unsigned: template-15 {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for J784S4 board";
description = UBOOT_BOARD_DESCRIPTION;
};
fdt-0 {
description = "k3-j784s4-evm";
description = BOARD_DESCRIPTION;
type = "flat_dt";
arch = "arm";
compression = "none";
j784s4_evm_dtb_unsigned: blob {
filename = J784S4_EVM_DTB;
filename = "u-boot.dtb";
};
hash {
@@ -350,7 +315,7 @@
default = "conf-0";
conf-0 {
description = "k3-j784s4-evm";
description = BOARD_DESCRIPTION;
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
@@ -359,23 +324,4 @@
};
};
};
#include "k3-binman-capsule.dtsi"
// Capsule update GUIDs in string form. See j784s4_evm.h
#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e"
#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617"
&capsule_tispl {
efi-capsule {
image-guid = AM69_SK_SPL_IMAGE_GUID_STR;
};
};
&capsule_uboot {
efi-capsule {
image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR;
};
};
#endif

13256
arch/arm/dts/k3-j784s4-ddr.dtsi
View File

File diff suppressed because it is too large Load Diff

75
arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
View File

@@ -3,8 +3,83 @@
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#define SPL_BOARD_DTB "spl/dts/ti/k3-j784s4-evm.dtb"
#define BOARD_DESCRIPTION "k3-j784s4-evm"
#define UBOOT_BOARD_DESCRIPTION "U-Boot for J784S4 board"
#include "k3-j784s4-binman.dtsi"
#if defined(CONFIG_CPU_V7R)
&binman {
tiboot3-j784s4-hs {
insert-template = <&tiboot3_j784s4_hs>;
filename = "tiboot3-j784s4-hs-evm.bin";
};
tiboot3-j784s4-hs-fs {
insert-template = <&tiboot3_j784s4_hs_fs>;
filename = "tiboot3-j784s4-hs-fs-evm.bin";
};
tiboot3-j784s4-gp {
insert-template = <&tiboot3_j784s4_gp>;
filename = "tiboot3-j784s4-gp-evm.bin";
symlink = "tiboot3.bin";
};
};
&ti_fs_gp {
filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
};
&ti_fs_enc {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
};
&sysfw_inner_cert {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
};
&ti_fs_enc_fs {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
};
&sysfw_inner_cert_fs {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
};
#else // CONFIG_ARM64
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
tispl {
insert-template = <&ti_spl>;
};
u-boot {
insert-template = <&u_boot>;
};
tispl-unsigned {
insert-template = <&ti_spl_unsigned>;
};
u-boot-unsigned {
insert-template = <&u_boot_unsigned>;
};
};
#endif
/ {
memory@80000000 {
bootph-all;

4448
arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

14
arch/arm/dts/mt7987-pinctrl.dtsi
View File

@@ -191,6 +191,20 @@
};
};
pwm_pins: pwm-pins {
mux {
/*
* - pwm0 : PWM0@PIN13
* - pwm1_0 : PWM1@PIN7 (share with JTAG)
* pwm1_1 : PWM1@PIN43 (share with i2c0)
* - pwm2_0 : PWM2@PIN12 (share with PCM)
* pwm2_1 : PWM2@PIN44 (share with i2c0)
*/
function = "pwm";
groups = "pwm0";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";

16
arch/arm/dts/mt7987.dtsi
View File

@@ -389,21 +389,15 @@
};
pwm: pwm@10048000 {
compatible = "mediatek,mt7988-pwm";
compatible = "mediatek,mt7987-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
<&infracfg CLK_INFRA_66M_PWM_HCK>,
<&clkxtal>,
<&clkxtal>,
<&clkxtal>,
<&clkxtal>,
<&clkxtal>,
<&clkxtal>,
<&clkxtal>,
<&clkxtal>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
"pwm4","pwm5","pwm6","pwm7","pwm8";
<&infracfg CLK_INFRA_66M_PWM_HCK>,
<&infracfg CLK_INFRA_66M_PWM_HCK>,
<&infracfg CLK_INFRA_66M_PWM_HCK>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};

4
arch/arm/dts/mt7987a-u-boot.dtsi
View File

@@ -24,6 +24,10 @@
mediatek,hwver = <&hwver>;
};
};
reserved-memory {
/delete-node/ wmcpu-reserved@50000000;
};
};
&i2c0 {

4
arch/arm/dts/mt7987a.dtsi
View File

@@ -29,7 +29,7 @@
&fan {
pwms = <&pwm 0 50000 0>;
status = "okay";
status = "disabled";
};
&i2c0 {
@@ -59,6 +59,8 @@
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};

12
arch/arm/dts/nuvoton-common-npcm7xx.dtsi
View File

@@ -95,6 +95,11 @@
compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
reg = <0x801000 0x6C>;
};
timer0: timer@f0801068 {
compatible = "nuvoton,npcm750-timer";
reg = <0x801068 0x8>;
};
};
ahb {
@@ -245,13 +250,6 @@
status = "disabled";
};
timer0: timer@8000 {
compatible = "nuvoton,npcm750-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x1C>;
clocks = <&clk NPCM7XX_CLK_TIMER>;
};
watchdog0: watchdog@801C {
compatible = "nuvoton,npcm750-wdt";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

149
arch/arm/dts/sam9x60.dtsi
View File

@@ -17,6 +17,7 @@
/{
model = "Microchip SAM9X60 SoC";
compatible = "microchip,sam9x60";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
@@ -122,8 +123,6 @@
assigned-clock-rates = <100000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0>;
};
sdhci1: sdhci-host@90000000 {
@@ -135,8 +134,6 @@
assigned-clock-rates = <100000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1>;
};
apb {
@@ -176,8 +173,6 @@
macb0: ethernet@f802c000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
clock-names = "hclk", "pclk";
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
status = "disabled";
@@ -199,11 +194,17 @@
reg = <0xffffea00 0x100>;
};
aic: interrupt-controller@fffff100 {
compatible = "microchip,sam9x60-aic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xfffff100 0x100>;
atmel,external-irqs = <31>;
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
clock-names = "usart";
};
@@ -211,101 +212,65 @@
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "microchip,sam9x60-pinctrl", "simple-bus";
compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x800>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
0xfffffa00 0x200>; /* pioD */
/* shared pinctrl settings */
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
atmel,mux-mask = <
/* A B C */
0xffffffff 0xffe03fff 0xef00019d /* pioA */
0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
0xffffffff 0xffffffff 0xf83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <26>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A
(AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */
AT91_PIOA 16 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */
AT91_PIOA 15 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */
AT91_PIOA 18 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */
AT91_PIOA 19 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */
AT91_PIOA 20 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
sdhci1 {
pinctrl_sdhci1: sdhci1 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
#gpio-cells = <2>;
gpio-controller;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
#gpio-cells = <2>;
gpio-controller;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
#gpio-cells = <2>;
gpio-controller;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
#gpio-cells = <2>;
gpio-controller;
clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
};
pmc: pmc@fffffc00 {
compatible = "microchip,sam9x60-pmc";
reg = <0xfffffc00 0x200>;

213
arch/arm/dts/sam9x60ek.dts
View File

@@ -78,79 +78,15 @@
};
};
};
pinctrl {
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_ebi_addr_nand: ebi-addr-0 {
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
};
pinctrl_qspi: qspi {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_flx0: flx0_default {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_onewire_tm_default: onewire_tm_default {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
};
};
};
&dbgu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
@@ -218,9 +154,148 @@
&macb0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "okay";
};
&pinctrl {
/* shared pinctrl settings */
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
qspi {
pinctrl_qspi: qspi {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
};
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_ebi_addr_nand: ebi-addr-0 {
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
};
flexcom {
pinctrl_flx0: flx0_default {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
};
pinctrl_onewire_tm_default: onewire_tm_default {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A
(AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */
AT91_PIOA 16 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */
AT91_PIOA 15 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */
AT91_PIOA 18 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */
AT91_PIOA 19 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */
AT91_PIOA 20 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
};
};
sdhci1 {
pinctrl_sdhci1: sdhci1 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
};
};
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0>;
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1>;
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0

116
arch/arm/dts/sama5d3.dtsi
View File

@@ -492,12 +492,6 @@
0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
0xffffffff 0xbf9f8000 0x18000000 /* pioE */
>;
reg = <0xfffff200 0x100 /* pioA */
0xfffff400 0x100 /* pioB */
0xfffff600 0x100 /* pioC */
0xfffff800 0x100 /* pioD */
0xfffffa00 0x100 /* pioE */
>;
/* shared pinctrl settings */
adc0 {
@@ -873,66 +867,66 @@
AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
};
};
};
pioA: gpio@fffff200 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x100>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioA: gpio@fffff200 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x100>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x100>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x100>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x100>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x100>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x100>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
bootph-all;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x100>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
bootph-all;
};
pioE: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x100>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioE_clk>;
bootph-all;
pioE: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x100>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioE_clk>;
bootph-all;
};
};
pmc: pmc@fffffc00 {

118
arch/arm/dts/sama5d4.dtsi
View File

@@ -1361,62 +1361,6 @@
status = "disabled";
};
pioA: gpio@fc06a000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc06a000 0x100>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
};
pioB: gpio@fc06b000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc06b000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
};
pioC: gpio@fc06c000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc06c000 0x100>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pioD: gpio@fc068000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc068000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
};
pioE: gpio@fc06d000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc06d000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioE_clk>;
};
pinctrl@fc06a000 {
bootph-all;
#address-cells = <1>;
@@ -1433,12 +1377,62 @@
0x0003ff00 0x8002a800 0x00000000 /* pioD */
0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
>;
reg = < 0xfc06a000 0x100
0xfc06b000 0x100
0xfc06c000 0x100
0xfc068000 0x100
0xfc06d000 0x100
>;
pioA: gpio@fc06a000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc06a000 0x100>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
};
pioB: gpio@fc06b000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc06b000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
};
pioC: gpio@fc06c000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc06c000 0x100>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pioD: gpio@fc068000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc068000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
};
pioE: gpio@fc06d000 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfc06d000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioE_clk>;
};
/* pinctrl pin settings */
adc0 {

661
arch/arm/dts/socfpga_agilex5-u-boot.dtsi
View File

@@ -3,6 +3,7 @@
* U-Boot additions
*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
* Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_soc64_fit-u-boot.dtsi"
@@ -13,6 +14,659 @@
#size-cells = <2>;
bootph-all;
};
soc {
bootph-all;
socfpga_ccu_config: socfpga-ccu-config {
compatible = "intel,socfpga-dtreg";
#address-cells = <1>;
#size-cells = <1>;
bootph-all;
/* DSU */
i_ccu_caiu0@1c000000 {
reg = <0x1c000000 0x00001000>;
intel,offset-settings =
/* CAIUMIFSR */
<0x000003c4 0x00000000 0x07070777>,
/* DII1_MPFEREGS */
<0x00000414 0x00018000 0xffffffff>,
<0x00000418 0x00000000 0x000000ff>,
<0x00000410 0xc0e00200 0xc1f03e1f>,
/* DII2_GICREGS */
<0x00000424 0x0001d000 0xffffffff>,
<0x00000428 0x00000000 0x000000ff>,
<0x00000420 0xc0800400 0xc1f03e1f>,
/* NCAIU0_LWSOC2FPGA */
<0x00000444 0x00020000 0xffffffff>,
<0x00000448 0x00000000 0x000000ff>,
<0x00000440 0xc1100006 0xc1f03e1f>,
/* NCAIU0_SOC2FPGA_1G */
<0x00000454 0x00040000 0xffffffff>,
<0x00000458 0x00000000 0x000000ff>,
<0x00000450 0xc1200006 0xc1f03e1f>,
/* DMI_SDRAM_2G */
<0x00000464 0x00080000 0xffffffff>,
<0x00000468 0x00000000 0x000000ff>,
/* NCAIU0_SOC2FPGA_16G */
<0x00000474 0x00400000 0xffffffff>,
<0x00000478 0x00000000 0x000000ff>,
<0x00000470 0xc1600006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000484 0x00800000 0xffffffff>,
<0x00000488 0x00000000 0x000000ff>,
/* NCAIU0_SOC2FPGA_256G */
<0x00000494 0x04000000 0xffffffff>,
<0x00000498 0x00000000 0x000000ff>,
<0x00000490 0xc1a00006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a4 0x08000000 0xffffffff>,
<0x000004a8 0x00000000 0x000000ff>;
bootph-all;
};
/* FPGA2SOC */
i_ccu_ncaiu0@1c001000 {
reg = <0x1c001000 0x00001000>;
intel,offset-settings =
/* NCAIU0MIFSR */
<0x000003c4 0x00000000 0x07070777>,
/* PSS */
<0x00000404 0x00010000 0xffffffff>,
<0x00000408 0x00000000 0x000000ff>,
<0x00000400 0xC0F00000 0xc1f03e1f>,
/* DII1_MPFEREGS */
<0x00000414 0x00018000 0xffffffff>,
<0x00000418 0x00000000 0x000000ff>,
<0x00000410 0xc0e00200 0xc1f03e1f>,
/* NCAIU0_LWSOC2FPGA */
<0x00000444 0x00020000 0xffffffff>,
<0x00000448 0x00000000 0x000000ff>,
<0x00000440 0xc1100006 0xc1f03e1f>,
/* NCAIU0_SOC2FPGA_1G */
<0x00000454 0x00040000 0xffffffff>,
<0x00000458 0x00000000 0x000000ff>,
<0x00000450 0xc1200006 0xc1f03e1f>,
/* DMI_SDRAM_2G */
<0x00000464 0x00080000 0xffffffff>,
<0x00000468 0x00000000 0x000000ff>,
/* NCAIU0_SOC2FPGA_16G */
<0x00000474 0x00400000 0xffffffff>,
<0x00000478 0x00000000 0x000000ff>,
<0x00000470 0xc1600006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000484 0x00800000 0xffffffff>,
<0x00000488 0x00000000 0x000000ff>,
/* NCAIU0_SOC2FPGA_256G */
<0x00000494 0x04000000 0xffffffff>,
<0x00000498 0x00000000 0x000000ff>,
<0x00000490 0xc1a00006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a4 0x08000000 0xffffffff>,
<0x000004a8 0x00000000 0x000000ff>;
bootph-all;
};
/* GIC_M */
i_ccu_ncaiu1@1c002000 {
reg = <0x1c002000 0x00001000>;
intel,offset-settings =
/* NCAIU1MIFSR */
<0x000003c4 0x00000000 0x07070777>,
/* DMI_SDRAM_2G */
<0x00000464 0x00080000 0xffffffff>,
<0x00000468 0x00000000 0x000000ff>,
/* DMI_SDRAM_30G */
<0x00000484 0x00800000 0xffffffff>,
<0x00000488 0x00000000 0x000000ff>,
/* DMI_SDRAM_480G */
<0x000004a4 0x08000000 0xffffffff>,
<0x000004a8 0x00000000 0x000000ff>;
bootph-all;
};
/* SMMU */
i_ccu_ncaiu2@1c003000 {
reg = <0x1c003000 0x00001000>;
intel,offset-settings =
/* NCAIU2MIFSR */
<0x000003c4 0x00000000 0x07070777>,
/* DMI_SDRAM_2G */
<0x00000464 0x00080000 0xffffffff>,
<0x00000468 0x00000000 0x000000ff>,
/* DMI_SDRAM_30G */
<0x00000484 0x00800000 0xffffffff>,
<0x00000488 0x00000000 0x000000ff>,
/* DMI_SDRAM_480G */
<0x000004a4 0x08000000 0xffffffff>,
<0x000004a8 0x00000000 0x000000ff>;
bootph-all;
};
/* PSS NOC */
i_ccu_ncaiu3@1c004000 {
reg = <0x1c004000 0x00001000>;
intel,offset-settings =
/* NCAIU3MIFSR */
<0x000003c4 0x00000000 0x07070777>,
/* DII1_MPFEREGS */
<0x00000414 0x00018000 0xffffffff>,
<0x00000418 0x00000000 0x000000ff>,
<0x00000410 0xc0e00200 0xc1f03e1f>,
/* DMI_SDRAM_2G */
<0x00000464 0x00080000 0xffffffff>,
<0x00000468 0x00000000 0x000000ff>,
/* DMI_SDRAM_30G */
<0x00000484 0x00800000 0xffffffff>,
<0x00000488 0x00000000 0x000000ff>,
/* DMI_SDRAM_480G */
<0x000004a4 0x08000000 0xffffffff>,
<0x000004a8 0x00000000 0x000000ff>;
bootph-all;
};
/* DCE0 */
i_ccu_dce0@1c005000 {
reg = <0x1c005000 0x00001000>;
intel,offset-settings =
/* DCEUMIFSR0 */
<0x000003c4 0x00000000 0x07070777>,
/* DMI_SDRAM_2G */
<0x00000464 0x00080000 0xffffffff>,
<0x00000468 0x00000000 0x000000ff>,
/* DMI_SDRAM_30G */
<0x00000484 0x00800000 0xffffffff>,
<0x00000488 0x00000000 0x000000ff>,
/* DMI_SDRAM_480G */
<0x000004a4 0x08000000 0xffffffff>,
<0x000004a8 0x00000000 0x000000ff>;
bootph-all;
};
/* DCE1 */
i_ccu_dce1@1c006000 {
reg = <0x1c006000 0x00001000>;
intel,offset-settings =
/* DCEUMIFSR1 */
<0x000003c4 0x00000000 0x07070777>,
/* DMI_SDRAM_2G */
<0x00000464 0x00080000 0xffffffff>,
<0x00000468 0x00000000 0x000000ff>,
/* DMI_SDRAM_30G */
<0x00000484 0x00800000 0xffffffff>,
<0x00000488 0x00000000 0x000000ff>,
/* DMI_SDRAM_480G */
<0x000004a4 0x08000000 0xffffffff>,
<0x000004a8 0x00000000 0x000000ff>;
bootph-all;
};
/* DMI0 */
i_ccu_dmi0@1c007000 {
reg = <0x1c007000 0x00001000>;
intel,offset-settings =
/* DMIUSMCTCR */
<0x00000300 0x00000001 0x00000003>,
<0x00000300 0x00000003 0x00000003>;
bootph-all;
};
/* DMI1 */
i_ccu_dmi0@1c008000 {
reg = <0x1c008000 0x00001000>;
intel,offset-settings =
/* DMIUSMCTCR */
<0x00000300 0x00000001 0x00000003>,
<0x00000300 0x00000003 0x00000003>;
bootph-all;
};
};
socfpga_firewall_config: socfpga-firewall-config {
compatible = "intel,socfpga-dtreg";
#address-cells = <1>;
#size-cells = <1>;
bootph-all;
/* L4 peripherals firewall */
noc_fw_l4_per@10d21000 {
reg = <0x10d21000 0x0000008c>;
intel,offset-settings =
/* NAND */
<0x00000000 0x01010001 0x01010001>,
/* USB0 */
<0x0000000c 0x01010001 0x01010001>,
/* USB1 */
<0x00000010 0x01010001 0x01010001>,
/* SPI_MAIN0 */
<0x0000001c 0x01010301 0x01010301>,
/* SPI_MAIN1 */
<0x00000020 0x01010301 0x01010301>,
/* SPI_SECONDARY0 */
<0x00000024 0x01010301 0x01010301>,
/* SPI_SECONDARY1 */
<0x00000028 0x01010301 0x01010301>,
/* EMAC0 */
<0x0000002c 0x01010001 0x01010001>,
/* EMAC1 */
<0x00000030 0x01010001 0x01010001>,
/* EMAC2 */
<0x00000034 0x01010001 0x01010001>,
/* SDMMC */
<0x00000040 0x01010001 0x01010001>,
/* GPIO0 */
<0x00000044 0x01010301 0x01010301>,
/* GPIO1 */
<0x00000048 0x01010301 0x01010301>,
/* I2C0 */
<0x00000050 0x01010301 0x01010301>,
/* I2C1 */
<0x00000054 0x01010301 0x01010301>,
/* I2C2 */
<0x00000058 0x01010301 0x01010301>,
/* I2C3 */
<0x0000005c 0x01010301 0x01010301>,
/* I2C4 */
<0x00000060 0x01010301 0x01010301>,
/* SP_TIMER0 */
<0x00000064 0x01010301 0x01010301>,
/* SP_TIMER1 */
<0x00000068 0x01010301 0x01010301>,
/* UART0 */
<0x0000006c 0x01010301 0x01010301>,
/* UART1 */
<0x00000070 0x01010301 0x01010301>,
/* I3C0 */
<0x00000074 0x01010301 0x01010301>,
/* I3C1 */
<0x00000078 0x01010301 0x01010301>,
/* DMA0 */
<0x0000007c 0x01010001 0x01010001>,
/* DMA1 */
<0x00000080 0x01010001 0x01010001>,
/* COMBO_PHY */
<0x00000084 0x01010001 0x01010001>,
/* NAND_SDMA */
<0x00000088 0x01010301 0x01010301>;
bootph-all;
};
/* L4 system firewall */
noc_fw_l4_sys@10d21100 {
reg = <0x10d21100 0x00000098>;
intel,offset-settings =
/* DMA_ECC */
<0x00000008 0x01010001 0x01010001>,
/* EMAC0RX_ECC */
<0x0000000c 0x01010001 0x01010001>,
/* EMAC0TX_ECC */
<0x00000010 0x01010001 0x01010001>,
/* EMAC1RX_ECC */
<0x00000014 0x01010001 0x01010001>,
/* EMAC1TX_ECC */
<0x00000018 0x01010001 0x01010001>,
/* EMAC2RX_ECC */
<0x0000001c 0x01010001 0x01010001>,
/* EMAC2TX_ECC */
<0x00000020 0x01010001 0x01010001>,
/* NAND_ECC */
<0x0000002c 0x01010001 0x01010001>,
/* NAND_READ_ECC */
<0x00000030 0x01010001 0x01010001>,
/* NAND_WRITE_ECC */
<0x00000034 0x01010001 0x01010001>,
/* OCRAM_ECC */
<0x00000038 0x01010001 0x01010001>,
/* SDMMC_ECC */
<0x00000040 0x01010001 0x01010001>,
/* USB0_ECC */
<0x00000044 0x01010001 0x01010001>,
/* USB1_CACHEECC */
<0x00000048 0x01010001 0x01010001>,
/* CLOCK_MANAGER */
<0x0000004c 0x01010001 0x01010001>,
/* IO_MANAGER */
<0x00000054 0x01010001 0x01010001>,
/* RESET_MANAGER */
<0x00000058 0x01010001 0x01010001>,
/* SYSTEM_MANAGER */
<0x0000005c 0x01010001 0x01010001>,
/* OSC0_TIMER */
<0x00000060 0x01010301 0x01010301>,
/* OSC1_TIMER0*/
<0x00000064 0x01010301 0x01010301>,
/* WATCHDOG0 */
<0x00000068 0x01010301 0x01010301>,
/* WATCHDOG1 */
<0x0000006c 0x01010301 0x01010301>,
/* WATCHDOG2 */
<0x00000070 0x01010301 0x01010301>,
/* WATCHDOG3 */
<0x00000074 0x01010301 0x01010301>,
/* DAP */
<0x00000078 0x03010001 0x03010001>,
/* WATCHDOG4 */
<0x0000007c 0x01010301 0x01010301>,
/* POWER_MANAGER */
<0x00000080 0x01010001 0x01010001>,
/* USB1_RXECC */
<0x00000084 0x01010001 0x01010001>,
/* USB1_TXECC */
<0x00000088 0x01010001 0x01010001>,
/* L4_NOC_PROBES */
<0x00000090 0x01010001 0x01010001>,
/* L4_NOC_QOS */
<0x00000094 0x01010001 0x01010001>;
bootph-all;
};
/* Light weight SoC2FPGA */
noc_fw_lwsoc2fpga@10d21300 {
reg = <0x10d21300 0x0000004>;
intel,offset-settings =
/* LWSOC2FPGA_CSR */
<0x00000000 0x0ffe0301 0x0ffe0301>;
bootph-all;
};
/* SoC2FPGA */
noc_fw_soc2fpga@10d21200 {
reg = <0x10d21200 0x0000004>;
intel,offset-settings =
/* SOC2FPGA_CSR */
<0x00000000 0x0ffe0301 0x0ffe0301>;
bootph-all;
};
/* TCU */
noc_fw_tcu@10d21400 {
reg = <0x10d21400 0x0000004>;
intel,offset-settings =
/* TCU_CSR */
<0x00000000 0x01010001 0x01010001>;
bootph-all;
};
};
socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off {
compatible = "intel,socfpga-dtreg";
#address-cells = <1>;
#size-cells = <1>;
bootph-all;
/* DSU */
i_ccu_caiu0@1c000000 {
reg = <0x1c000000 0x00001000>;
intel,offset-settings =
/* CAIUAMIGR */
<0x000003c0 0x00000003 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81300006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81700006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81b00006 0xc1f03e1f>;
bootph-all;
};
/* FPGA2SOC */
i_ccu_ncaiu0@1c001000 {
reg = <0x1c001000 0x00001000>;
intel,offset-settings =
/* NCAIU0AMIGR */
<0x000003c0 0x00000003 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81300006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81700006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81b00006 0xc1f03e1f>;
bootph-all;
};
/* GIC_M */
i_ccu_ncaiu1@1c002000 {
reg = <0x1c002000 0x00001000>;
intel,offset-settings =
/* NCAIU1AMIGR */
<0x000003c0 0x00000003 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81300006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81700006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81b00006 0xc1f03e1f>;
bootph-all;
};
/* SMMU */
i_ccu_ncaiu2@1c003000 {
reg = <0x1c003000 0x00001000>;
intel,offset-settings =
/* NCAIU2AMIGR */
<0x000003c0 0x00000003 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81300006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81700006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81b00006 0xc1f03e1f>;
bootph-all;
};
/* PSS NOC */
i_ccu_ncaiu3@1c004000 {
reg = <0x1c004000 0x00001000>;
intel,offset-settings =
/* NCAIU3AMIGR */
<0x000003c0 0x00000003 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81300006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81700006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81b00006 0xc1f03e1f>;
bootph-all;
};
/* DCE0 */
i_ccu_dce0@1c005000 {
reg = <0x1c005000 0x00001000>;
intel,offset-settings =
/* DCEUAMIGR0 */
<0x000003c0 0x00000003 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81300006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81700006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81b00006 0xc1f03e1f>;
bootph-all;
};
/* DCE1 */
i_ccu_dce1@1c006000 {
reg = <0x1c006000 0x00001000>;
intel,offset-settings =
/* DCEUAMIGR1 */
<0x000003c0 0x00000003 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81300006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81700006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81b00006 0xc1f03e1f>;
bootph-all;
};
};
socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on {
compatible = "intel,socfpga-dtreg";
#address-cells = <1>;
#size-cells = <1>;
bootph-all;
/* DSU */
i_ccu_caiu0@1c000000 {
reg = <0x1c000000 0x00001000>;
intel,offset-settings =
/* CAIUAMIGR */
<0x000003c0 0x00000001 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81200006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81600006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81a00006 0xc1f03e1f>;
bootph-all;
};
/* FPGA2SOC */
i_ccu_ncaiu0@1c001000 {
reg = <0x1c001000 0x00001000>;
intel,offset-settings =
/* NCAIU0AMIGR */
<0x000003c0 0x00000001 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81200006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81600006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81a00006 0xc1f03e1f>;
bootph-all;
};
/* GIC_M */
i_ccu_ncaiu1@1c002000 {
reg = <0x1c002000 0x00001000>;
intel,offset-settings =
/* NCAIU1AMIGR */
<0x000003c0 0x00000001 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81200006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81600006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81a00006 0xc1f03e1f>;
bootph-all;
};
/* SMMU */
i_ccu_ncaiu2@1c003000 {
reg = <0x1c003000 0x00001000>;
intel,offset-settings =
/* NCAIU2AMIGR */
<0x000003c0 0x00000001 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81200006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81600006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81a00006 0xc1f03e1f>;
bootph-all;
};
/* PSS NOC */
i_ccu_ncaiu3@1c004000 {
reg = <0x1c004000 0x00001000>;
intel,offset-settings =
/* NCAIU3AMIGR */
<0x000003c0 0x00000001 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81200006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81600006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81a00006 0xc1f03e1f>;
bootph-all;
};
/* DCE0 */
i_ccu_dce0@1c005000 {
reg = <0x1c005000 0x00001000>;
intel,offset-settings =
/* DCEUAMIGR0 */
<0x000003c0 0x00000001 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81200006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81600006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81a00006 0xc1f03e1f>;
bootph-all;
};
/* DCE1 */
i_ccu_dce1@1c006000 {
reg = <0x1c006000 0x00001000>;
intel,offset-settings =
/* DCEUAMIGR1 */
<0x000003c0 0x00000001 0x0000001f>,
/* DMI_SDRAM_2G */
<0x00000460 0x81200006 0xc1f03e1f>,
/* DMI_SDRAM_30G */
<0x00000480 0x81600006 0xc1f03e1f>,
/* DMI_SDRAM_480G */
<0x000004a0 0x81a00006 0xc1f03e1f>;
bootph-all;
};
};
socfpga_smmu_secure_config: socfpga-smmu-secure-config {
compatible = "intel,socfpga-dtreg";
#address-cells = <1>;
#size-cells = <1>;
bootph-all;
/* System manager */
i_sys_mgt_sysmgr_csr@10d12000 {
reg = <0x10d12000 0x00000500>;
intel,offset-settings =
/* dma_tbu_stream_ctrl_reg_0_dma0 */
<0x0000017c 0x00000000 0x0000003f>,
/* dma_tbu_stream_ctrl_reg_0_dma1 */
<0x00000180 0x00000000 0x0000003f>,
/* sdm_tbu_stream_ctrl_reg_1_sdm */
<0x00000184 0x00000000 0x0000003f>,
/* io_tbu_stream_ctrl_reg_2_usb2 */
<0x00000188 0x00000000 0x0000003f>,
/* io_tbu_stream_ctrl_reg_2_sdmmc */
<0x00000190 0x00000000 0x0000003f>,
/* io_tbu_stream_ctrl_reg_2_nand */
<0x00000194 0x00000000 0x0000003f>,
/* io_tbu_stream_ctrl_reg_2_etr */
<0x00000198 0x00000000 0x0000003f>,
/* tsn_tbu_stream_ctrl_reg_3_tsn0 */
<0x0000019c 0x00000000 0x0000003f>,
/* tsn_tbu_stream_ctrl_reg_3_tsn1 */
<0x000001a0 0x00000000 0x0000003f>,
/* tsn_tbu_stream_ctrl_reg_3_tsn2 */
<0x000001a4 0x00000000 0x0000003f>;
bootph-all;
};
};
socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr {
compatible = "intel,socfpga-dtreg";
#address-cells = <1>;
#size-cells = <1>;
bootph-all;
/* noc fw mpfe csr */
i_noc_fw_mpfe_csr@18000d00 {
reg = <0x18000d00 0x00000100>;
intel,offset-settings =
/* mpfe scr io96b0 reg*/
<0x00000000 0x00000001 0x00010101>,
/* mpfe scr io96b1 reg*/
<0x00000004 0x00000001 0x00010101>,
/* mpfe scr noc csr*/
<0x00000008 0x00000001 0x00010101>;
bootph-all;
};
};
};
};
&clkmgr {
@@ -57,6 +711,13 @@
bootph-all;
};
&sdr {
compatible = "intel,sdr-ctl-agilex5";
reg = <0x18000000 0x400000>;
resets = <&rst DDRSCH_RESET>;
bootph-all;
};
&sysmgr {
compatible = "altr,sys-mgr", "syscon";
bootph-all;

22
arch/arm/dts/socfpga_agilex5.dtsi
View File

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
* Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
/dts-v1/;
@@ -330,6 +331,20 @@
status = "disabled";
};
nand: nand@10b80000 {
compatible = "cdns,nand";
reg = <0x10b80000 0x10000>,
<0x10840000 0x1000>;
reg-names = "reg", "sdma";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 97 4>;
clocks = <&clkmgr AGILEX5_NAND_CLK>;
resets = <&rst NAND_RESET>, <&rst COMBOPHY_RESET>;
cdns,board-delay-ps = <4830>;
status = "disabled";
};
ocram: sram@00000000 {
compatible = "mmio-sram";
reg = <0x00000000 0x200000>;
@@ -544,6 +559,13 @@
status = "disabled";
};
sdr: sdr@18000000 {
compatible = "intel,sdr-ctl-agilex5";
reg = <0x18000000 0x400000>;
resets = <&rst DDRSCH_RESET>;
bootph-all;
};
/* QSPI address not available yet */
qspi: spi@108d2000 {
compatible = "cdns,qspi-nor";

79
arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
View File

@@ -3,6 +3,7 @@
* U-Boot additions
*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
* Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_agilex5-u-boot.dtsi"
@@ -21,11 +22,38 @@
};
};
memory {
/* 8GB */
reg = <0 0x80000000 0 0x80000000>,
<8 0x80000000 1 0x80000000>;
};
/*
* Both Memory base address and size default info is retrieved from HW setting.
* Reconfiguration / Overwrite these info can be done with examples below.
*/
/*
* Example for memory size with 2GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>;
* };
*/
/*
* Example for memory size with 8GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x1 0x80000000>;
* };
*/
/*
* Example for memory size with 32GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x7 0x80000000>;
* };
*/
/*
* Example for memory size with 512GB:
* memory {
* reg = <0x0 0x80000000 0x0 0x80000000>,
* <0x8 0x80000000 0x7 0x80000000>,
* <0x88 0x00000000 0x78 0x00000000>;
* };
*/
chosen {
stdout-path = "serial0:115200n8";
@@ -41,6 +69,10 @@
/delete-property/ cdns,read-delay;
};
&flash1 {
bootph-all;
};
&i3c0 {
bootph-all;
};
@@ -102,6 +134,10 @@
status = "okay";
};
&nand {
bootph-all;
};
&timer0 {
bootph-all;
};
@@ -122,3 +158,36 @@
bootph-all;
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&emac0_phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwxgmac-mdio";
emac0_phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&gmac2 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwxgmac-mdio";
emac2_phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

23
arch/arm/dts/socfpga_agilex5_socdk.dts
View File

@@ -62,6 +62,10 @@
status = "okay";
};
&i2c3 {
status = "okay";
};
&i3c0 {
status = "okay";
};
@@ -161,3 +165,22 @@
};
};
};
&nand {
status = "okay";
flash1: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0 0x200000>;
};
partition@200000 {
label = "root";
reg = <0x200000 0x3fe00000>;
};
};
};

10
arch/arm/dts/stm32746g-eval-u-boot.dtsi
View File

@@ -22,16 +22,6 @@
mmc0 = &sdio1;
spi0 = &qspi;
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioc 13 0>;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpiof 10 0>;
};
};
&fmc {

10
arch/arm/dts/stm32f746-disco-u-boot.dtsi
View File

@@ -22,16 +22,6 @@
mmc0 = &sdio1;
spi0 = &qspi;
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpioi 1 0>;
};
};
&ltdc {

10
arch/arm/dts/stm32f769-disco-u-boot.dtsi
View File

@@ -23,16 +23,6 @@
spi0 = &qspi;
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioa 0 0>;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpioj 5 0>;
};
panel: panel {
compatible = "orisetech,otm8009a";
reset-gpios = <&gpioj 15 1>;

15
arch/arm/dts/stm32mp13-pinctrl.dtsi
View File

@@ -215,6 +215,21 @@
};
};
pwm1_ch3n_pins_a: pwm1-ch3n-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */
};
};
pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */

22
arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
View File

@@ -23,3 +23,25 @@
&usbphyc {
bootph-all;
};
&st33htph {
reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>;
};
/* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
&vdd_ldo2 {
bootph-all;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
&vdd_sd {
bootph-all;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};

14
arch/arm/dts/stm32mp135f-dk.dts
View File

@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
@@ -207,6 +208,19 @@
status = "disabled";
};
&timers1 {
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
pwm1: pwm {
pinctrl-0 = <&pwm1_ch3n_pins_a>;
pinctrl-1 = <&pwm1_ch3n_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
};
&timers3 {
/delete-property/dmas;
/delete-property/dma-names;

2
arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
View File

@@ -13,6 +13,8 @@
config {
dh,ddr3-coding-gpios = <&gpiod 5 0>, <&gpiod 9 0>;
dh,som-coding-gpios = <&gpioa 13 0>, <&gpioi 1 0>;
u-boot,mmc-env-offset = <0x3fc000>;
u-boot,mmc-env-offset-redundant = <0x3fc000>;
};
};

592
arch/arm/dts/tegra124-xiaomi-mocha.dts Normal file
View File

@@ -0,0 +1,592 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "tegra124.dtsi"
/ {
model = "Xiaomi Mi Pad A0101";
compatible = "xiaomi,mocha", "nvidia,tegra124";
chosen {
stdout-path = &uartd;
};
aliases {
i2c0 = &pwr_i2c;
i2c1 = &gen1_i2c;
mmc0 = &sdmmc4; /* eMMC */
mmc1 = &sdmmc3; /* uSD slot */
usb0 = &usb1;
};
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
host1x@50000000 {
dsia: dsi@54300000 {
status = "okay";
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
nvidia,ganged-mode = <&dsib>;
panel@0 {
compatible = "sharp,lq079l1sx01";
reg = <0>;
link2 = <&panel_secondary>;
avdd-supply = <&avdd_lcd>;
vddio-supply = <&vdd_lcd_io>;
vsp-supply = <&vsp_5v5_lcd>;
vsn-supply = <&vsn_5v5_lcd>;
reset-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_LOW>;
backlight = <&lp8556>;
};
};
dsib: dsi@54400000 {
status = "okay";
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
panel_secondary: panel@0 {
compatible = "sharp,lq079l1sx01";
reg = <0>;
};
};
};
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
/* Keys pinmux */
keys {
nvidia,pins = "kb_col0_pq0",
"kb_col6_pq6",
"kb_col7_pq7";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hall-front {
nvidia,pins = "pi5";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hall-back {
nvidia,pins = "gpio_w3_aud_pw3";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Leds pinmux */
bl-en {
nvidia,pins = "pbb4";
nvidia,function = "vgp4";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
keys-led {
nvidia,pins = "ph1";
nvidia,function = "pwm1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* Panel pinmux */
lcd-rst {
nvidia,pins = "ph3";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
lcd-vsp {
nvidia,pins = "pi4";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
lcd-vsn {
nvidia,pins = "kb_row10_ps2";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
lcd-id {
nvidia,pins = "kb_row6_pr6";
nvidia,function = "displaya_alt";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
lcd-pwm {
nvidia,pins = "ph2";
nvidia,function = "pwm2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
sdmmc3-clk {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
sdmmc3-cmd {
nvidia,pins = "sdmmc3_cmd_pa7",
"sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4",
"sdmmc3_clk_lb_out_pee4",
"sdmmc3_clk_lb_in_pee5";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
sdmmc3-cd {
nvidia,pins = "sdmmc3_cd_n_pv2";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
usd-pwr {
nvidia,pins = "kb_row0_pr0";
nvidia,function = "rsvd4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* SDMMC4 pinmux */
sdmmc4-clk {
nvidia,pins = "sdmmc4_clk_pcc4";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
sdmmc4-cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
"sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* I2C pinmux */
gen1-i2c {
nvidia,pins = "gen1_i2c_sda_pc5",
"gen1_i2c_scl_pc4";
nvidia,function = "i2c1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
"gen2_i2c_sda_pt6";
nvidia,function = "i2c2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
"cam_i2c_sda_pbb2";
nvidia,function = "i2c3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
"ddc_sda_pv5";
nvidia,function = "i2c4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
"pwr_i2c_sda_pz7";
nvidia,function = "i2cpwr";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dsi-b {
nvidia,pins = "mipi_pad_ctrl_dsi_b";
nvidia,function = "dsi_b";
};
/* GPIO power/drive control */
drive-sdio1 {
nvidia,pins = "drive_sdio1";
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <32>;
nvidia,pull-up-strength = <42>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
};
drive-sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <20>;
nvidia,pull-up-strength = <36>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
};
drive-gma {
nvidia,pins = "drive_gma";
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <1>;
nvidia,pull-up-strength = <2>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
};
};
};
uartd: serial@70006300 {
status = "okay";
};
gen1_i2c: i2c@7000c000 {
status = "okay";
clock-frequency = <400000>;
lp8556: backlight@2c {
compatible = "ti,lp8556";
reg = <0x2c>;
dev-ctrl = /bits/ 8 <0x83>;
init-brt = /bits/ 8 <0x1f>;
power-supply = <&vdd_3v3_sys>;
enable-supply = <&vddio_1v8_bl>;
rom-98h {
rom-addr = /bits/ 8 <0x98>;
rom-val = /bits/ 8 <0x80>;
};
rom-9eh {
rom-addr = /bits/ 8 <0x9e>;
rom-val = /bits/ 8 <0x21>;
};
rom-a0h {
rom-addr = /bits/ 8 <0xa0>;
rom-val = /bits/ 8 <0xff>;
};
rom-a1h {
rom-addr = /bits/ 8 <0xa1>;
rom-val = /bits/ 8 <0x3f>;
};
rom-a2h {
rom-addr = /bits/ 8 <0xa2>;
rom-val = /bits/ 8 <0x20>;
};
rom-a3h {
rom-addr = /bits/ 8 <0xa3>;
rom-val = /bits/ 8 <0x00>;
};
rom-a4h {
rom-addr = /bits/ 8 <0xa4>;
rom-val = /bits/ 8 <0x72>;
};
rom-a5h {
rom-addr = /bits/ 8 <0xa5>;
rom-val = /bits/ 8 <0x24>;
};
rom-a6h {
rom-addr = /bits/ 8 <0xa6>;
rom-val = /bits/ 8 <0x80>;
};
rom-a7h {
rom-addr = /bits/ 8 <0xa7>;
rom-val = /bits/ 8 <0xf5>;
};
rom-a8h {
rom-addr = /bits/ 8 <0xa8>;
rom-val = /bits/ 8 <0x24>;
};
rom-a9h {
rom-addr = /bits/ 8 <0xa9>;
rom-val = /bits/ 8 <0xb2>;
};
rom-aah {
rom-addr = /bits/ 8 <0xaa>;
rom-val = /bits/ 8 <0x8f>;
};
rom-aeh {
rom-addr = /bits/ 8 <0xae>;
rom-val = /bits/ 8 <0x0f>;
};
};
};
pwr_i2c: i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
/* Texas Instruments TPS65913 PMIC */
pmic: tps65913@58 {
compatible = "ti,tps65913";
reg = <0x58>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
palmas_gpio: gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
pinmux {
compatible = "ti,tps65913-pinctrl";
pinctrl-names = "default";
pinctrl-0 = <&palmas_default>;
palmas_default: pinmux {
pin_gpio4 {
pins = "gpio4";
function = "gpio";
};
};
};
pmic {
compatible = "ti,tps65913-pmic";
regulators {
vdd_1v8_vio: smps8 {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_hv_sdmmc: smps9 {
regulator-name = "vdd_hv_sdmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
avdd_lcd: ldo2 {
regulator-name = "avdd_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
avdd_dsi_csi: ldo5 {
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
};
vddio_usd: ldo9 {
regulator-name = "vddio_sdmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
avdd_usb: ldousb {
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
};
sdmmc3: sdhci@700b0400 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_hv_sdmmc>;
vqmmc-supply = <&vddio_usd>;
};
sdmmc4: sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
vmmc-supply = <&vdd_hv_sdmmc>;
vqmmc-supply = <&vdd_1v8_vio>;
};
usb1: usb@7d000000 {
status = "okay";
dr_mode = "otg";
};
clk32k_in: clock-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ref-oscillator";
};
extcon-keys {
compatible = "gpio-keys";
switch-back-hall-sensor {
label = "Hall sensor (back)";
gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
};
switch-front-hall-sensor {
label = "Hall sensor (front)";
gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
};
};
gpio-keys {
compatible = "gpio-keys";
key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
};
key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
};
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
};
};
vdd_3v3_sys: regulator-bl-en {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0_bl";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
};
vddio_1v8_bl: regulator-bl-io {
compatible = "regulator-fixed";
regulator-name = "vddio_1v8_bl";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
};
vdd_lcd_io: regulator-lcdvio {
compatible = "regulator-fixed";
regulator-name = "dvdd_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>;
};
vsp_5v5_lcd: regulator-vsp {
compatible = "regulator-fixed";
regulator-name = "avdd_lcd_vsp";
regulator-min-microvolt = <5500000>;
regulator-max-microvolt = <5500000>;
enable-active-high;
gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
};
vsn_5v5_lcd: regulator-vsn {
compatible = "regulator-fixed";
regulator-name = "avdd_lcd_vsn";
regulator-min-microvolt = <5500000>;
regulator-max-microvolt = <5500000>;
enable-active-high;
gpio = <&gpio TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
};
};

4
arch/arm/dts/tegra20-u-boot.dtsi
View File

@@ -9,5 +9,9 @@
dc@54200000 {
bootph-all;
};
dc@54240000 {
bootph-all;
};
};
};

40
arch/arm/dts/tegra30-asus-p1801-t.dts
View File

@@ -34,20 +34,10 @@
host1x@50000000 {
dc@54200000 {
clocks = <&tegra_car TEGRA30_CLK_DISP1>,
<&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
rgb {
status = "okay";
nvidia,panel = <&hdmi>;
};
status = "disabled";
};
hdmi: hdmi@54280000 {
clocks = <&tegra_car TEGRA30_CLK_HDMI>,
<&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
status = "okay";
hdmi-supply = <&hdmi_5v0_sys>;
@@ -118,8 +108,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -203,7 +193,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -213,7 +203,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -223,7 +213,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -232,7 +222,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -242,7 +232,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
nvidia,pins = "pu4";
@@ -260,7 +250,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hdmi_hpd {
nvidia,pins = "hdmi_int_pn7";
@@ -632,8 +622,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -718,8 +708,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_d10_pt2 {
nvidia,pins = "vi_d10_pt2",
@@ -838,8 +828,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {
nvidia,pins = "vi_mclk_pt1";

44
arch/arm/dts/tegra30-asus-tf600t.dts
View File

@@ -90,8 +90,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC2 pinmux */
@@ -107,8 +107,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -142,8 +142,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4_cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -159,8 +159,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4_rst_n {
nvidia,pins = "sdmmc4_rst_n_pcc3";
@@ -186,7 +186,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -196,7 +196,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -206,7 +206,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -215,7 +215,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -225,7 +225,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
nvidia,pins = "pu4";
@@ -243,7 +243,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hdmi_hpd {
nvidia,pins = "hdmi_int_pn7";
@@ -613,8 +613,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -701,8 +701,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
pbb0 {
nvidia,pins = "pbb0";
@@ -827,8 +827,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -836,8 +836,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
jtag {

96
arch/arm/dts/tegra30-asus-tf700t.dts
View File

@@ -15,7 +15,14 @@
rgb {
status = "okay";
nvidia,panel = <&tc358768>;
/delete-property/ nvidia,panel;
port {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;
};
};
};
};
};
@@ -118,38 +125,69 @@
vddio-supply = <&vdd_1v8_vio>;
vddmipi-supply = <&vdd_1v2_mipi>;
panel = <&panel>;
/*
* Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
* LCD SuperIPS+ Full HD panel.
*/
panel@1 {
compatible = "panasonic,vvx10f004b00";
reg = <1>;
power-supply = <&vdd_pnl_reg>;
backlight = <&backlight>;
display-timings {
timing@0 {
/* 1920x1200@60Hz */
clock-frequency = <154000000>;
hactive = <1920>;
hfront-porch = <48>;
hback-porch = <80>;
hsync-len = <32>;
hsync-active = <1>;
vactive = <1200>;
vfront-porch = <3>;
vback-porch = <26>;
vsync-len = <6>;
vsync-active = <1>;
};
};
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input: endpoint {
remote-endpoint = <&dpi_output>;
bus-width = <24>;
};
};
port@1 {
reg = <1>;
bridge_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
};
};
panel: panel {
compatible = "panasonic,vvx10f004b00";
power-supply = <&vdd_pnl_reg>;
backlight = <&backlight>;
/delete-property/ enable-gpios;
display-timings {
timing@0 {
/* 1920x1200@60Hz */
clock-frequency = <154000000>;
hactive = <1920>;
hfront-porch = <48>;
hback-porch = <80>;
hsync-len = <32>;
hsync-active = <1>;
vactive = <1200>;
vfront-porch = <3>;
vback-porch = <26>;
vsync-len = <6>;
vsync-active = <1>;
};
};
};
/delete-node/ panel;
vdd_1v2_mipi: regulator-mipi {
compatible = "regulator-fixed";

26
arch/arm/dts/tegra30-asus-transformer.dtsi
View File

@@ -99,8 +99,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -189,7 +189,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
@@ -200,7 +200,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
@@ -211,7 +211,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
@@ -221,7 +221,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
@@ -232,7 +232,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
@@ -647,8 +647,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -741,8 +741,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_d10_pt2 {
@@ -879,8 +879,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {

40
arch/arm/dts/tegra30-htc-endeavoru.dts
View File

@@ -33,13 +33,11 @@
host1x@50000000 {
dc@54200000 {
clocks = <&tegra_car TEGRA30_CLK_DISP1>,
<&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
backlight: backlight {
compatible = "nvidia,tegra-pwm-backlight";
rgb {
status = "okay";
nvidia,panel = <&dsia>;
nvidia,pwm-source = <1>;
nvidia,default-brightness = <0x8E>;
};
};
@@ -48,7 +46,17 @@
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
panel = <&panel>;
panel@0 {
compatible = "htc,edge-panel";
reg = <0>;
reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
vdd-supply = <&vdd_3v3_panel>;
vddio-supply = <&vdd_1v8_panel>;
backlight = <&backlight>;
};
};
};
@@ -1255,13 +1263,6 @@
nvidia,xcvr-lsrslew = <2>;
};
backlight: backlight {
compatible = "nvidia,tegra-pwm-backlight";
nvidia,pwm-source = <1>;
nvidia,default-brightness = <0x8E>;
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
@@ -1292,17 +1293,6 @@
};
};
panel: panel {
compatible = "htc,edge-panel";
reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
vdd-supply = <&vdd_3v3_panel>;
vddio-supply = <&vdd_1v8_panel>;
backlight = <&backlight>;
};
vcore_emmc: regulator-emmc {
compatible = "regulator-fixed";
regulator-name = "vdd_2v85_sdmmc";

46
arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
View File

@@ -109,8 +109,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4-cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -127,8 +127,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
cam-mclk {
nvidia,pins = "cam_mclk_pcc0";
@@ -147,7 +147,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -157,7 +157,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -167,7 +167,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -176,7 +176,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -186,7 +186,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */
@@ -724,8 +724,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-vsync-pd6 {
nvidia,pins = "vi_vsync_pd6",
@@ -736,8 +736,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <2>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_ENABLE>;
};
vi-hsync-pd7 {
nvidia,pins = "vi_hsync_pd7",
@@ -749,8 +749,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d2-pl0 {
nvidia,pins = "vi_d2_pl0",
@@ -760,8 +760,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-mclk-pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -769,8 +769,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <2>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_ENABLE>;
};
vi-d11-pt3 {
nvidia,pins = "vi_d11_pt3";
@@ -778,8 +778,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d5-pl3 {
nvidia,pins = "vi_d5_pl3";
@@ -787,8 +787,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* PORT U */

34
arch/arm/dts/tegra30-lg-p880.dts
View File

@@ -101,6 +101,31 @@
};
};
spi@7000dc00 {
bridge-spi@2 {
/*
* JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel
*/
panel@0 {
compatible = "jdi,dx12d100vm0eaa";
reg = <0>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
vdd-supply = <&vcc_3v0_lcd>;
vddio-supply = <&iovcc_1v8_lcd>;
backlight = <&backlight>;
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
};
};
sdmmc3: sdhci@78000400 {
status = "okay";
bus-width = <4>;
@@ -118,13 +143,4 @@
linux,code = <KEY_UP>;
};
};
panel: panel {
compatible = "jdi,dx12d100vm0eaa";
enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
};
};

47
arch/arm/dts/tegra30-lg-p895.dts
View File

@@ -108,36 +108,37 @@
};
};
panel: panel {
compatible = "hitachi,tx13d100vm0eaa";
spi@7000dc00 {
bridge-spi@2 {
/*
* HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel
*/
panel@0 {
compatible = "koe,tx13d100vm0eaa";
reg = <0>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
renesas,gamma = <3>;
renesas,inversion;
renesas,contrast;
renesas,gamma = <3>;
renesas,inversion;
renesas,contrast;
vcc-supply = <&vcc_3v0_lcd>;
iovcc-supply = <&iovcc_1v8_lcd>;
vcc-supply = <&vcc_3v0_lcd>;
iovcc-supply = <&iovcc_1v8_lcd>;
backlight = <&backlight>;
backlight = <&backlight>;
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
};
};
vcc_3v0_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "vcc_3v0_lcd";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-lcd3v {
gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
iovcc_1v8_lcd: regulator-lcdvio {
compatible = "regulator-fixed";
regulator-name = "iovcc_1v8_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

82
arch/arm/dts/tegra30-lg-x3.dtsi
View File

@@ -32,7 +32,12 @@
rgb {
status = "okay";
nvidia,panel = <&bridge>;
port {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;
};
};
};
};
};
@@ -890,12 +895,22 @@
status = "okay";
clock-frequency = <400000>;
backlight: lm3533@36 {
backlight: led-controller@36 {
compatible = "ti,lm3533";
reg = <0x36>;
enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
default-brightness-level = <128>;
ti,boost-ovp-microvolt = <24000000>;
ti,boost-freq-hz = <500000>;
backlight-0 {
compatible = "ti,lm3533-backlight";
ti,max-current-microamp = <23400>;
ti,linear-mapping-mode;
ti,hardware-controlled;
};
};
muic@44 {
@@ -969,18 +984,46 @@
compatible = "solomon,ssd2825";
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
spi-cpol;
spi-cpha;
spi-max-frequency = <1000000>;
power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>;
dvdd-supply = <&vdd_1v2_rgb>;
avdd-supply = <&vdd_1v2_rgb>;
vddio-supply = <&vdd_1v8_vio>;
solomon,hs-zero-delay-ns = <300>;
solomon,hs-prep-delay-ns = <65>;
clocks = <&ssd2825_refclk>;
clock-names = "tx_clk";
panel = <&panel>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input: endpoint {
remote-endpoint = <&dpi_output>;
bus-width = <24>;
};
};
port@1 {
reg = <1>;
bridge_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
};
@@ -1036,4 +1079,29 @@
linux,code = <KEY_DOWN>;
};
};
vdd_1v2_rgb: regulator-rgb1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vcc_3v0_lcd: regulator-lcd3v {
compatible = "regulator-fixed";
regulator-name = "vcc_3v0_lcd";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
iovcc_1v8_lcd: regulator-lcd1v8 {
compatible = "regulator-fixed";
regulator-name = "iovcc_1v8_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

38
arch/arm/dts/tegra30-microsoft-surface-rt.dts
View File

@@ -103,8 +103,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4-cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -121,8 +121,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
cam-mclk {
nvidia,pins = "cam_mclk_pcc0";
@@ -141,7 +141,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -151,7 +151,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -161,7 +161,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -170,7 +170,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -180,7 +180,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */
@@ -703,8 +703,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d3-pl1 {
nvidia,pins = "vi_d3_pl1";
@@ -712,8 +712,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-hsync-pd7 {
nvidia,pins = "vi_hsync_pd7",
@@ -724,8 +724,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-mclk-pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -733,8 +733,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d11-pt3 {
nvidia,pins = "vi_d11_pt3";
@@ -742,8 +742,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* PORT U */

2063
arch/arm/dts/tegra30-ouya.dts Normal file
View File

File diff suppressed because it is too large Load Diff

10
arch/arm/dts/tegra30-wexler-qc750.dts
View File

@@ -157,7 +157,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -167,7 +167,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -177,7 +177,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -186,7 +186,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -196,7 +196,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */

14
arch/arm/include/asm/arch-meson/boot.h
View File

@@ -21,4 +21,18 @@ int meson_get_boot_device(void);
int meson_get_soc_rev(char *buff, size_t buff_len);
/**
* meson_get_socinfo - retrieve cpu_id of the Amlogic SoC
*
* The value in the following format is read from register:
* +-----------+------------+------------+------------+
* | family_id | package_id | chip_rev | layout_rev |
* +-----------+------------+------------+------------+
* | 31 24 | 23 16 | 15 8 | 7 0 |
* +-----------+------------+------------+------------+
*
* Return: 4 bytes value of cpu_id on success or 0 on failure.
*/
u32 meson_get_socinfo(void);
#endif /* __MESON_BOOT_H__ */

48
arch/arm/include/asm/arch-meson/sm.h
View File

@@ -6,6 +6,8 @@
#ifndef __MESON_SM_H__
#define __MESON_SM_H__
#include <asm/types.h>
/**
* meson_sm_read_efuse - read efuse memory into buffer
*
@@ -27,16 +29,60 @@ ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size);
#define SM_SERIAL_SIZE 12
#define MESON_CPU_ID_SZ 4
#define MESON_CHIP_ID_SZ 16
/**
* meson_sm_get_serial - read chip unique id into buffer
* union meson_cpu_id - Amlogic cpu_id.
* @raw: buffer to hold the cpu_id value as sequential bytes.
* @val: cpu_id represented as 32 bit value.
*/
union meson_cpu_id {
u8 raw[MESON_CPU_ID_SZ];
u32 val;
};
/**
* struct meson_sm_chip_id - Amlogic chip_id.
* @cpu_id: cpu_id value, which is distinct from socinfo in that the order of
* PACK & MINOR bytes are swapped according to Amlogic chip_id format.
* @serial: 12 byte unique SoC number, identifying particular die, read
* usually from efuse OTP storage. Serial comes in little-endian
* order.
*/
struct meson_sm_chip_id {
union meson_cpu_id cpu_id;
u8 serial[SM_SERIAL_SIZE];
};
/**
* meson_sm_get_serial - read chip unique serial (OTP data) into buffer
*
* @buffer: pointer to buffer
* @size: buffer size.
*
* Serial is returned in big-endian order.
*
* @return: zero on success or -errno on failure
*/
int meson_sm_get_serial(void *buffer, size_t size);
/**
* meson_sm_get_chip_id - read Amlogic chip_id
*
* @chip_id: pointer to buffer capable to hold the struct meson_sm_chip_id
*
* Amlogic SoCs support 2 versions of chip_id. Function requests the newest
* one (v2), but if chip_id v2 is not supported, then secure monitor returns
* v1. All differences between v1 and v2 versions are handled by this function
* and chip_id is returned in unified format.
*
* chip_id contains serial, which is returned here in little-endian order.
*
* @return: 0 on success or -errno on failure
*/
int meson_sm_get_chip_id(struct meson_sm_chip_id *chip_id);
enum {
REBOOT_REASON_COLD = 0,
REBOOT_REASON_NORMAL = 1,

18
arch/arm/include/asm/arch-npcm8xx/gmac.h Normal file
View File

@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef _NPCM_GMAC_H_
#define _NPCM_GMAC_H_
/* PCS registers */
#define PCS_BA 0xF0780000
#define PCS_IND_AC 0x1FE
#define SR_MII_MMD 0x3E0000
#define SR_MII_MMD_CTRL 0x0
#define SR_MII_MMD_STS 0x2
#define VR_MII_MMD 0x3F0000
#define VR_MII_MMD_CTRL1 0x0
#define VR_MII_MMD_AN_CTRL 0x2
#define LINK_UP_TIMEOUT (3 * CONFIG_SYS_HZ)
#endif

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