Commit Graph

99951 Commits

Author SHA1 Message Date
Tom Rini
b62e422d6e mmc: Kconfig: Really correct dependencies SDHCI ADMA options
When doing the investigation for commit 53bb8fdea1 ("mmc: Kconfig:
Correct dependencies SDHCI ADMA options") I missed the implications of
MMC_SDHCI_ADMA_HELPERS. The problem is that FSL_ESDHC via the
FSL_ESDHC_SUPPORT_ADMA2 option will also enable these helper functions.
This in turn means the correct dependency here is
MMC_SDHCI_ADMA_HELPERS and not *MMC_SDHCI_ADMA.

Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-11 18:29:25 -06:00
Tom Rini
730201c6f5 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
One more board to support, this time Retronix Sparrow Hawk based on
Renesas R-Car V4H SoC . This is board support, so master branch should
be fine. The DT in dts/upstream/ is a backport from Linux, and will
disappear on next DT sync.
2025-06-10 16:32:17 -06:00
Marek Vasut
55c4a6db54 arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support
Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0
(R8A779G3) SoC. This is a single-board computer with single gigabit ethernet,
DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports,
micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD,
debug UART and JTAG.

DT is imported from Linux next commit:
a719915e76f2 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support")

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-10 20:50:50 +02:00
Marek Vasut
91729f824b arm64: renesas: Introduce renesas_dram_init_banksize()
Introduce weak renesas_dram_init_banksize() function which is meant
to be used to adjust DRAM bank sizes after the common Renesas board
DRAM bank handling code finished. This is mainly meant for boards
which ship with multiple DRAM size options, which can be detected
at runtime. This allows such boards to ship with single U-Boot
binary on all boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-10 20:50:50 +02:00
Tom Rini
d7c449c3d8 Prepare v2025.07-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-09 15:54:18 -06:00
Heinrich Schuchardt
51ec8db232 pylibfdt: correct license information
Setuptools 78.1.1 shows warnings:

* Pattern 'GPL' did not match any files.
* Pattern 'BSD-2-Clause' did not match any files.
* SetuptoolsDeprecationWarning: License classifiers are deprecated.

Cf. https://packaging.python.org/en/latest/guides/writing-pyproject-toml/#license

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-09 14:07:21 -06:00
Fabio Estevam
b492f9520c Revert "caam: Fix CAAM error on startup"
This reverts commit 159b6f0e11.

Since commit 159b6f0e11 ("caam: Fix CAAM error on startup") the following
regression was reported by Tim Harvey:

"I've found that this patch causes a regression on an imx8mm board
(imx8mm_venice_defconfig) where the first call to caam_rng_read fails
here in jr_dequeue but if you call it again it works. With some
debugging added:
SEC0:  RNG instantiated
...
Hit any key to stop autoboot:  0
u-boot=> rng list
RNG #0 - caam-rng
u-boot=> rng 0 10
caam_rng_read caam-rng len=16
run_descriptor_jr_idx idx=0
Error in SEC deq: -1
caam_rng_read_one run_descriptor_jr failed: -1
caam_rng_read caam-rng caam_rng_read_one failed: -5
Reading RNG failed
u-boot=> rng 0 10
caam_rng_read caam-rng len=16
run_descriptor_jr_idx idx=0
00000000: ad 2e ad c0 2a 12 27 c4 65 82 66 19 be ef f6 07  ....*.'.e.f.....

If I revert your patch caam_rng_read works initially and on subsequent
calls."

" I ran into this when I was testing
lwIP HTTPS as it causes anything that uses dm_rng to fail the first
time (such as HTTPS)."

Revert it for now to avoid the regression.

Reported-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-06-09 11:01:24 -06:00
Tom Rini
89ee2ce3f9 configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-09 09:32:19 -06:00
Tom Rini
7966c78429 Merge patch series "arm: armv7: fix a bug that prevents CONFIG_BLOBLIST and CONFIG_POSITION_INDEPENDENT to be enabled together"
Yang Xiwen <forbidden405@outlook.com> says:

This patchset also enables CONFIG_POSITION_INDEPENDENT for qemu boards
to avoid similar issues to happen again in the future.

Link: https://lore.kernel.org/r/20250531-pie_blob_fix-v1-0-7b4a37987dbc@outlook.com
2025-06-09 09:18:26 -06:00
Yang Xiwen
0a7610c97a arm: qemu: Add imply CONFIG_POSITION_INDEPENDENT
Add 'imply CONFIG_POSITION_INDEPENTDENT' for QEMU arm arch. This allows
qemu arm boards to load u-boot.bin at any address. It is skipped by
default when u-boot is loaded by either --bios or --kernel.

To load u-boot.bin at a different address, one can use u-boot
chain-loading or qemu loader device[1].

[1] https://www.qemu.org/docs/master/system/generic-loader.html

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2025-06-09 09:18:17 -06:00
Yang Xiwen
03005fbe50 arm: armv7: restore section to .text after saved_args
when CONFIG_BLOBLIST is enabled, the section is switched to .data but is
not switched back to .text. It makes all the code below placed in .data
section, also breaks CONFIG_POSITION_INDEPENDENT.

Fix it by adding `.section .text` to switch the section back to .text.

Fixes: 5103e69344 ("arm: armv7: save boot arguments")
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2025-06-09 09:18:17 -06:00
Tom Rini
a854c12062 Merge tag 'u-boot-rockchip-20250606' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/26117

- Allow to silent TPL/SPL debug console;
- enable exFAT support for Theobroma boards;
- Fix SD power initialization in SPL for rk3399-nanopi4
2025-06-08 09:24:08 -06:00
Tom Rini
5a8dd2e0c8 Merge tag 'doc-2025-07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2025-07-rc4

Documentation:

* fix typo in gcc.rst
* correct EFI_TCG2_PROTOCOL_MEASURE_DTB description
* Add missing reference to firmware for BB-AI64
* Tidy up the bootefi-command docs
2025-06-07 08:18:54 -06:00
BehradElmi
2018486f6c doc: build: fix typo in gcc.rst
Fix a typo error in gcc.rst, changing "out-out-tree" to
"out-of-tree" in the Out-of-tree section.

Signed-off-by: BehradElmi <behradelmi1@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-06-07 14:52:18 +02:00
Simon Glass
e108a0f6d9 doc: efi_loader: Tidy up the bootefi-command docs
There are backslashes in some of the tags which seems to be unnecessary.
Remove then.

Change the word 'either' to 'any' since there are three options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-06-07 14:52:18 +02:00
Peter Robinson
abc8fd1014 doc: board: ti: Add missing firmware for BB-AI64
The details of the sysfw.itb from the R5 build that
also needs to be copied as part of the target images
is missing, but is included in the image formats a
little further down, so add it to the instructions.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
2025-06-07 14:52:18 +02:00
Heinrich Schuchardt
5bbfaea4d4 efi_loader: correct EFI_TCG2_PROTOCOL_MEASURE_DTB description
%s/data that change/data that changes/
%s/cannot be used has/cannot be used for/
%s/Otherwise/Otherwise,/
%s/allows better measurement/allows for better measurement/

Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-06-07 14:52:18 +02:00
Quentin Schulz
b8101af3ce power: rk8xx: fix swapped mask and value in init registers for RK806
The val (the bits to set) is the second member of the reg_data structure
and mask the third one. We obviously want to clear bits 6 and 7 in order
to only set bit 7 in there instead of only clearing bit 7 in order to
write bits 6 and 7 (which makes no sense).

Fortunately, according to the datasheet, bit 6 value doesn't matter when
bit 7 is set so this is essentially just a cosmetic change, no intended
change in behavior.

Fixes: f172575d92 ("power: rk8xx: add support for RK806")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:23:34 +08:00
Justin Klaassen
210ab4f60d rockchip: rk3399-nanopi-4: Enable IO-domain driver in SPL
The NanoPi RK3399 boards support UHS-I (up to SDR104) SD cards, however
using any of these 1.8v modes results in a boot failure in SPL upon soft
reboot.

The issue is that the "vcc_sdio" regulator is left at 1.8v on reboot
and the corresponding GPIO defaults to 3.3v. This prevents the SD card
from being reinitialized and read successfully.

This change enables the RK8XX regulators and Rockchip IO-domain drivers
in SPL, which initializes "vcc_sdio" regulator to 3.0v and configures
the GPIO for the correct level on boot.

Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:21:54 +08:00
Justin Klaassen
2abd7fff9e rockchip: rk3399-nanopi-4: Allow MMC driver to control SD regulators
This change removes the "regulator-always-on" property from the
"vcc3v0_sd" (vmmc-supply) and "vcc_sdio" (vqmmc-supply) regulators,
which otherwise prevents the MMC driver from being able to power cycle
the SD card as part of the initialization procedure.

It also removes the "regulator-boot-on" from the "vcc_sdio" regulator,
which could theoretically damage a SD card that is already initialized
in a low voltage mode.

Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:21:54 +08:00
Justin Klaassen
f8f865ec0b regulator: rk8xx: Add CONFIG_SPL_REGULATOR_RK8XX
Allows use of the regulator functions of the RK8XX PMIC in SPL, which is
necessary to support the functionality of the Rockchip IO-domain driver
on relevant platforms.

Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:21:54 +08:00
Justin Klaassen
83b1d04765 rockchip: io-domain: Add CONFIG_SPL_ROCKCHIP_IODOMAIN
Allows use of the Rockchip IO-domain driver in SPL to configure
the GPIO to match the voltage supplied by specific regulators
(e.g. "vcc_sdio").

Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:21:54 +08:00
Justin Klaassen
81a26131bd rockchip: io-domain: Add debug logging for regulators during probe
Log the value of the regulators during initialization of the IO-domain
driver to aid in debugging GPIO voltage configuration problems.

Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:21:54 +08:00
Quentin Schulz
4aa110d73e configs: puma-rk3399: enable exFAT support
Our upcoming Mass Flasher solution will be storing boot artifacts on an
exFAT partition so enable its support.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Quentin Schulz
369e86a98a configs: tiger-rk3588: enable exFAT support
Our upcoming Mass Flasher solution will be storing boot artifacts on an
exFAT partition so enable its support.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Quentin Schulz
41edb09cd0 configs: jaguar-rk3588: enable exFAT support
Our upcoming Mass Flasher solution will be storing boot artifacts on an
exFAT partition so enable its support.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Quentin Schulz
fd11e10c96 configs: ringneck-px30: enable exFAT support
Our upcoming Mass Flasher solution will be storing boot artifacts on an
exFAT partition so enable its support.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Lukasz Czechowski
ac86ee45ee rockchip: px30: Fix hard dependency to DEBUG_UART_BOARD_INIT
Because DEBUG_UART_BOARD_INIT depends on DEBUG_UART, hard dependency
to DEBUG_UART_BOARD_INIT in ROCKCHIP_PX30 can cause warnings if
DEBUG_UART is disabled.
The DEBUG_UART_BOARD_INIT is already implied by ARCH_ROCKCHIP entry.
Remove hard dependency from ROCKCHIP_PX30, so that it will be
consistent with other rockchip boards.

Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Lukasz Czechowski
80bac23430 rockchip: px30: Weaken dependency TPL/SPL serial
Allow to disable serial console in TPL and SPL. Weak dependency
to SPL_SERIAL and TPL_SERIAL is also used in other Rockchip boards.

Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Lukasz Czechowski
0fb68337f2 debug_uart: Replace debug functions with dummies if CONFIG_DEBUG_UART is not set
In case DEBUG UART is not used, define dummy macros replacing
the actual function implementations that will not be available.
This allows to compile code and avoid linker errors.
Redefine the DEBUG_UART_FUNCS macro if DEBUG UART is not available,
to avoid compilation errors.

Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Lukasz Czechowski
6773a46f11 ram: rockchip: Fix dependency of RAM_ROCKCHIP_DEBUG
The RAM_ROCKCHIP_DEBUG can be used only if DEBUG_UART is
available.
The next commit introduces changes in definition of debug
uart functions, so that DEBUG_UART is required to be defined
in order to initialize uart and use print functions.

Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-06-06 17:12:20 +08:00
Lukasz Czechowski
c1f9995d82 efi: stub: Change _debug_uart_putc function to inline
Update definition of _debug_uart_putc to static inline.
This will allow to avoid compilation warnings about unused code
after introduction of patch changing debug uart functions to
dummies if CONFIG_DEBUG_UART is not set.
This also matches the instructions in include/debug_uart.h and
provides consistency with implementations for other platforms.

Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Lukasz Czechowski
79d9ac8b13 arm: uniphier: Change _debug_uart_putc function to inline
Update the definition of _debug_uart_putc to static inline.
This matches the instructions in include/debug_uart.h and
provides consistency with implementations for other platforms.

Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-06-06 17:12:20 +08:00
Tom Rini
b3f69c1418 Merge tag 'xilinx-for-v2025.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2025.07-rc4

usb:
- Fix regulator handling

net:
- Fix MII clock handling

phy:
- Fix GTR line logic for sgmii

pci:
- Fix pcireg_base logic

fpga:
- Fix change handling in intel_sdm_mb driver
2025-06-05 08:40:42 -06:00
Anshul Dalal
27cd65ca1b mach-k3: am62ax: enable caches for the SPL stage
board_init_f for the am62a is missing the call to spl_enable_cache which
exists for all other am62 platforms (check am625_init.c &
am62p5_init.c).

This allows the usage of caches while loading and parsing the u-boot.img
FIT resulting in ~2x speedup in the A53 SPL stage.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-06-04 12:27:57 -06:00
Andrew Davis
5262b3ab93 board: ti: am62ax: env: Use default MMC related args
There are common MMC args for TI plats in include/environment/ti/mmc.env.
Since we already include this, there is no need to redefine these
MMC vars. Use the defaults.

This seems like something that could have been done while refactoring
these vars in the first place as it happened after this AM62A file
was available hence the fixes tag.

Reported-by: Chirag Shilwant <c-shilwant@ti.com>
Fixes: 3709b52915 ("env: ti: mmc.env: Move mmc related args to common place")
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Acked-by: Chirag Shilwant <c-shilwant@ti.com>
Reviewed-by: Judith Mendez <jm@ti.com>
2025-06-04 11:58:11 -06:00
Judith Mendez
2782ce5fce mmc: am654_sdhci: Clear UHS_MODE_SELECT when <= MMC_HS_52
This clears UHS_MODE_SELECT for timing modes <= MMC_HS_52.

When initializing to HS400 mode, the host controller downgrades to non-uhs
modes so clear UHS_MODE_SELECT at modes <= MMC_HS_52.

This fixes eMMC writes on j7200 EVM.

Fixes: 6067aa66b3 ("mmc: am654_sdhci: Add am654_sdhci_set_control_reg")
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-06-04 11:50:39 -06:00
Simon Glass
4ef863f2d6 x86: Correct condition for init_cache_f_r()
The condition here is reversed, which makes link and coral very slow,
leading to lab failures.

Fixes 6c171f7a18 ("common: board: make initcalls static")

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-06-04 08:15:12 -06:00
Padmarao Begari
77b053502f usb: onboard-hub: Fix return type for regulator APIs
Apart from ENOENT observing return value as ENOSYS when
!DM_REGULATOR that's why cover both configurations.
Changed code is not working as operation should be "&&"
not "||" (ret != -ENOENT && ret != -ENOSYS).

Also fix the remove function where the regulator_set_enable_if_allowed()
function is returning an error.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a2d520f14efc30fc28ec59881205e156dabbfcd9.1744350937.git.michal.simek@amd.com
2025-06-04 10:24:16 +02:00
Tom Rini
fdc0dcbb2c Merge tag 'qcom-more-for-2025.07' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
More Qualcomm fixes for 2025.07

* Adjust fdtfile logic to support more boards
* Support linux,code variable in qcom-pmic button driver
* Minor CLK API adjustments and apq8096/msm8916 fixes
* vbus regulator register fixes
* dragonboard410c KASLR support and other fixes
2025-06-03 09:00:52 -06:00
Patrick Rudolph
d1555de5fa arm/dts/qemu-sbsa: Fix interrupt
Change the vcpumntirq in the GICv3 node from SPI to PPI.

Prevents Linux from complaining:
'[Firmware Bug]: CPU interface incapable of MMIO access'

Fixes: 6d722894fd "board: emulation: Add QEMU sbsa support"

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2025-06-02 14:58:46 -06:00
Tom Rini
afb3ab64cb scripts/spelling.txt: Sync script with kernel v6.15
Keep spelling.txt in sync with the version from kernel v6.15.

Reported-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 10:26:04 -06:00
Sumit Garg
14315b73a8 mach-snapdragon: Update fdtfile logic to work for RB1 and RB2
RB1 and RB2 have three root compatibles where the last one can't be used
to decode fdtfile name (qcm* vs qrb*). So rather just rely on the first
compatible to retrieve the SoC name.

Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250505124333.12344-1-sumit.garg@kernel.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02 18:20:40 +02:00
Alexey Minnekhanov
c92bf21e73 button: qcom-pmic: allow to specify code in devicetree
Most device vendors put "Volume Down" button onto PMIC RESIN.
But Sony is special: see
dts/upstream/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi or [1].
They put "Volume Down" on PMIC GPIO 7 where others usually put
"Volume Up", and KEY_VOLUMEUP is inside &pon_resin.

Currently if you boot U-Boot on such Sony device, you end up
with 2 "Volume Down" buttons, and no "Volume Up", which makes
navigating menu problematic.

Support reading devicetree "linux,code" property and override
statically defined button code & label based on that.

[1] https://elixir.bootlin.com/linux/v6.15-rc3/source/arch/
arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi#L263

Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Signed-off-by: Alexey Minnekhanov <alexeymin@minlexx.ru>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424014811.3809818-1-alexeymin@minlexx.ru
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02 18:20:33 +02:00
Stephan Gerhold
1079d4bf2e clk: qcom: apq8016: Fix SDCC clock warnings
As of commit dc8754e8e4 ("clk/qcom: apq8016: improve clk_enable logging")
there are now warnings in the U-Boot console on DragonBoard 410c:

  apq8016_clk_enable: unknown clk id 122
  apq8016_clk_enable: unknown clk id 123
  apq8016_clk_enable: unknown clk id 124
  apq8016_clk_enable: unknown clk id 125

This is because we don't implement enable() properly for the SDCC clocks.
Currently they are being enabled as part of set_rate().

Fix this by moving the enable calls out of the apq8016_clk_init_sdc()
function and convert them to the equivalent GATE_CLK_POLLED() definitions.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-6-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02 18:20:16 +02:00
Stephan Gerhold
9d9bac00bc clk: qcom: apq8016: Convert GATE_CLK() to GATE_CLK_POLLED()
Convert the usages of GATE_CLK() in clock-apq8016 to GATE_CLK_POLLED() to
make sure that we poll the status when enabling clocks:

 - PRNG_AHB_CLK is a vote clock, so we poll a different register address.
 - The USB clocks are simple branches, so enable/poll is the same register.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-5-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02 18:20:15 +02:00
Stephan Gerhold
6c049ed993 clk: qcom: Allow polling for clock status in qcom_gate_clk_en()
GATE_CLK() in its current state is unsafe: A simple write to the clock
enable register does not guarantee that the clock is immediately running.
Without polling the clock status, we may issue writes to registers before
the necessary clocks start running. This doesn't seem to cause issues in
U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A
for the SMMU clocks on DB410c reliably triggers an exception during boot.

Make it possible to poll the branch clock status register, by adding a new
GATE_CLK_POLLED() macro that takes the extra register address. Existing
usages work just as before, without polling the clock status. Ideally all
usages should be updated to specify the correct poll address in the future.

The Qualcomm naming for these clocks is "branch" and not "gate", but let's
keep the existing naming for now to avoid confusion until all others
drivers have been converted.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-4-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02 18:20:15 +02:00
Stephan Gerhold
94e57ba201 clk: qcom: Use setbits_le32() for qcom_gate_clk_en()
The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02 18:20:15 +02:00
Stephan Gerhold
409da8c493 clk: qcom: Move qcom_gate_clk_en() to C file
This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02 18:20:15 +02:00
Stephan Gerhold
3d9e6d42ca clk: qcom: apq8016: Fix SDCC clock addresses
The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses:

 - SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018
   Should be 0x42018, this is an invalid register close to the USB clocks.
 - SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018
   Should be 0x43018, this is the SDCC1 clock.

When we try to enable SDCC2, we actually end up enabling SDCC1. When we try
to enable SDCC1, we just issue some broken register writes.

This hasn't caused any trouble so far, because the boot firmware is keeping
both SDCC clocks running. However, if these clocks are disabled when
entering U-Boot, MMC initialization is failing.

Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was
already correct, but change it the same way for consistency.

Fixes: 085921368b ("arm: Add support for Qualcomm Snapdragon family")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02 18:20:15 +02:00