app: stacked_cores: 46-xx: complete some runs of an inverter cascaded into a buffer

the results aren't great :'(

Cargo.lock

@@ -2058,6 +2058,7 @@ name = "stacked_cores"
 version = "0.1.0"
 dependencies = [
  "coremem",
+ "log",
 ]
 
 [[package]]

crates/applications/stacked_cores/Cargo.toml

@@ -6,3 +6,4 @@ edition = "2021"
 
 [dependencies]
 coremem = { path = "../../coremem" }
+log = "0.4"

crates/applications/stacked_cores/scripts/plot_inverters.py

@@ -132,6 +132,7 @@ of_interest += [(p, get_meas(p)) for p in
 
 
 # plot all viable inverters
+of_interest += filter_meas(run="40")
 # of_interest += filter_meas(run="41", viable_inverter=True)
 # of_interest += filter_meas(run="42", rad_um=400, couplings=4)
 # of_interest += filter_meas(run="42", rad_um=400, couplings=9)
@@ -139,18 +140,28 @@ of_interest += [(p, get_meas(p)) for p in
 # of_interest += filter_meas(run="42", rad_um=400, couplings=6)
 # of_interest += filter_meas(run="43")
 
-for (inv_p, inv_curve) in filter_meas(is_inverter=True):
+# plot cascaded inverter -> buffer
-    for (fwd_p, fwd_curve) in filter_meas(rad_um=400, is_inverter=False):
+# for (inv_p, inv_curve) in filter_meas(is_inverter=True):
-        of_interest += [ (SimParamsCascaded(inv_p, fwd_p), inv_curve.cascaded(fwd_curve)) ]
+#     for (fwd_p, fwd_curve) in filter_meas(rad_um=400, is_inverter=False):
+#         of_interest += [ (SimParamsCascaded(inv_p, fwd_p), inv_curve.cascaded(fwd_curve)) ]
+# plot cascaded buffer -> inverter
+# for (fwd_p, fwd_curve) in filter_meas(run="41", is_inverter=False):
+#     for (inv_p, inv_curve) in filter_meas(is_inverter=True):
+#         of_interest += [ (SimParamsCascaded(fwd_p, inv_p), fwd_curve.cascaded(inv_curve)) ]
 
+# of_interest += filter_meas(is_inverter=False)
+# of_interest += filter_meas(is_inverter=True)
 
 # of_interest.sort(key = lambda i: -i[1].max_abs_slope())
-# of_interest.sort(key = lambda i: -i[1].get_range())
+of_interest.sort(key = lambda i: -i[1].get_range())  # output range
-of_interest.sort(key = lambda i: i[1].get_repeated(1.0) - i[1].get_repeated(0.0))  # inverter strength
+# of_interest.sort(key = lambda i: i[1].get(0.5) - i[1].get(1.0))  # delayed output swing
+# of_interest.sort(key = lambda i: i[1].get(0.5) - i[1].get(0.0))  # early output swing
+# of_interest.sort(key = lambda i: i[1].get_repeated(1.0) - i[1].get_repeated(0.0))  # inverter strength
 
 for (params, curve) in of_interest[:5]:
     curve.plot(title = f"{params.human_name} mapping")
     curve.plot_slope(title = f"{params.human_name} slope")
-    if not params.is_inverter:
+    # if not params.is_inverter:
-        curve = curve.logically_inverted()
+    #     curve = curve.logically_inverted()
-    curve.plot_equilibrium(title = f"{params.human_name} equilibrium")
+    if params.is_inverter:
+        curve.plot_equilibrium(title = f"{params.human_name} equilibrium")

crates/applications/stacked_cores/scripts/stacked_cores_40xx_db.py

@@ -118,6 +118,19 @@ class SimParams43(SimParams):
     def t_last(self) -> float:
         return 5e-9
 
+class SimParams46(SimParams):
+    @property
+    def run(self) -> str:
+        return "46"
+
+    @property
+    def is_inverter(self) -> bool:
+        return True
+
+    @property
+    def t_last(self) -> float:
+        return 5e-9
+
 
 sims = [
     # params, human friendly db name, normalization
@@ -247,6 +260,14 @@ sims = [
     (SimParams43(4,  2, 600,  "1e10"), None, 20000),
     (SimParams43(4,  2, 600,  "2e10"), None, 20000),
     (SimParams43(4,  2, 600,  "30000001024e0"), None, 20000),  # 3e10
+
+    (SimParams46(5,  1, 400,  "5e9"),  None, 20000),
+    (SimParams46(5,  1, 400,  "8e9"),  None, 20000),
+    (SimParams46(5,  1, 400,  "1e10"), None, 20000),
+    (SimParams46(5,  1, 400,  "2e10"), None, 20000),
+    (SimParams46(5,  1, 400,  "4e10"), None, 20000),
+    (SimParams46(7,  1, 600,  "1e10"), None, 20000),
+    (SimParams46(4,  2, 600,  "2e10"), None, 20000),
 ]
 
 measurements = { real.machine_name: [human, norm, None, None] for (real, human, norm) in sims }
@@ -3581,4 +3602,49 @@ Piecewise(
 )
 """)
 
+set_meas("46-0.0004rad-5coupling-3_1_winding-5e9-drive", """
+Piecewise(
+    [
+        [ -16747,   -259 ],  # -1.0
+        [  16702,  -1813 ],  # 1.0
+    ]
+)
+""")
+
+set_meas("46-0.0004rad-5coupling-3_1_winding-8e9-drive", """
+Piecewise(
+    [
+        [ -16810,   9403 ],  # -1.0
+        [  16766,   7366 ],  # 1.0
+    ]
+)
+""")
+
+set_meas("46-0.0004rad-5coupling-3_1_winding-1e10-drive", """
+Piecewise(
+    [
+        [ -16834,  15248 ],  # -1.0
+        [  16776,  12945 ],  # 1.0
+    ]
+)
+""")
+
+set_meas("46-0.00059999997rad-7coupling-3_1_winding-1e10-drive", """
+Piecewise(
+    [
+        [ -16841,  13439 ],  # -1.0
+        [  16808,  11127 ],  # 1.0
+    ]
+)
+""")
+
+set_meas("46-0.00059999997rad-4coupling-5_1_winding-2e10-drive", """
+Piecewise(
+    [
+        [ -16778,  15097 ],  # -1.0
+        [  16802,  12503 ],  # 1.0
+    ]
+)
+""")
+
 if __name__ == '__main__': main()

crates/applications/stacked_cores/src/main.rs

@@ -36,6 +36,7 @@ use coremem::stim::{
     TimeVaryingExt as _,
 };
 use coremem::Driver;
+use log::info;
 
 // type R = real::R32;
 type R = f32;
@@ -1096,6 +1097,25 @@ fn drive_map_3stack_with_init_44(amp0: f32) -> [[ClockState; 3]; 7] {
     ]
 }
 
+#[allow(unused)]
+fn drive_map_3stack_with_init_inv_then_buff(amp0: f32) -> [[ClockState; 3]; 5] {
+    use ClockState as C;
+    // amplitudes are inverted from what you would expect.
+    // hold(-1) puts the core into a positive M
+    [
+        // init S0; charge S1 positive, S2 *negative*
+        [C::hold(-amp0),    C::hold_low(),    C::hold_high()],
+        // let the cores settle; open S1 for receive
+        [C::release(-amp0), C::release_low(), C::hold_high()],
+        // write S0 -> S1.
+        [C::hold_high(),    C::float(),       C::hold_high()],
+        // open S2 for receive
+        [C::hold_high(),    C::float(),       C::release_high()],
+        // write S1 -> S2
+        [C::hold_high(),    C::hold_high(),   C::float()],
+    ]
+}
+
 #[allow(unused)]
 fn drive_map_4stack_with_init4(amp0: f32, amp1: f32, amp2: f32, amp3: f32) -> [[ClockState; 4]; 3] {
     use ClockState as C;
@@ -1307,6 +1327,41 @@ fn couple_asymmetric_inverter(params: &Params, sender: u32, loops: u32, slot_off
     params
 }
 
+/// couple `sender` to the `sender+1` core by using `loops` loops, without any crossover.
+/// when sender goes high -> low, receiver goes low -> high ("buffering").
+/// `loops` must be >= 1.
+fn couple_asymmetric_buffer(params: &Params, sender: u32, loops: u32, slot_offset: u32, net_slots: u32) -> Params {
+    let c0 = sender;
+    let slots_per_asym = 2*loops;
+    // couple c to c+1
+    let c1 = c0+1;
+    let mut params = params
+        .with_coupling(c0, c1, slot_offset,                      net_slots, CouplingMethod::direct_half_exterior())
+        .with_coupling(c0, c1, slot_offset + slots_per_asym - 1, net_slots, CouplingMethod::direct_half_interior())
+    ;
+
+    // "loops" for receiver c1
+    // this connects the two ends of the input
+    for i in 0..slots_per_asym - 1 {
+        params = params.with_coupling(c1, c1, slot_offset + i, net_slots, CouplingMethod::SelfAngularTop);
+    }
+
+    // loops for sender c0:
+    for i in 0..loops {
+        if i != 0 {
+            // bridge this loop to the previous one
+            params = params.with_coupling(c0, c0, slot_offset + 2*i - 1, net_slots, CouplingMethod::SelfAngularBot);
+        }
+        params = params
+            .with_coupling(c0, c0, slot_offset + 2*i,     net_slots, CouplingMethod::SelfLoopHalfInterior)
+            .with_coupling(c0, c0, slot_offset + 2*i,     net_slots, CouplingMethod::SelfAngularTop)
+            .with_coupling(c0, c0, slot_offset + 2*i + 1, net_slots, CouplingMethod::SelfLoopHalfExterior)
+        ;
+    }
+
+    params
+}
+
 fn main() {
     coremem::init_logging();
     // coremem::init_debug();
@@ -4721,7 +4776,7 @@ fn main() {
         }
     }
 
-    if true {
+    if false {
         let p45xx = params_v2
             .with_clock_phase_duration(ps(1000))
             .with_clock_decay(ps(50))
@@ -4809,6 +4864,65 @@ fn main() {
             }
         }
     }
+
+    if true {
+        let p46xx = params_v2
+            .with_clock_phase_duration(ps(1000))
+            .with_clock_decay(ps(50))
+            .with_ctl_conductivity(5e2)
+            .with_coupling_conductivity(5e3)
+        ;
+        for init_set in [
+            &[
+                // establish the domain/range
+                 1.00,
+                -1.00,
+            ][..],
+            &[
+                 0.00,
+                 0.20,
+                -0.20,
+                 0.10,
+                -0.10,
+                 0.35,
+                -0.35,
+            ][..],
+        ] {
+            for (coupling_loops, s0_loops, s_major, cur_flt) in [
+                (5,  1, um(400),  1e10),  // verified geom;
+                (7,  1, um(600),  1e10),
+                (5,  1, um(400),  5e9),
+                (4,  2, um(600),  2e10),
+                (5,  1, um(400),  8e9),
+                (5,  1, um(400),  2e10),
+                (5,  1, um(400),  4e10),
+            ] {
+                for &init_flt in init_set {
+                    // coupling loops (M0 -> M1) + (M1 -> M2) + control slots
+                    let slots_per_asym = 2*s0_loops;
+                    let net_slots = 2*slots_per_asym + 1;
+                    let mut params = p46xx
+                        .with_s_major(s_major)
+                        .with_coupling_loops(coupling_loops)
+                        .with_input_magnitude(cur_flt)
+                        // control loops
+                        .with_coupling(0, 0, 0, net_slots, CouplingMethod::Control)
+                        .with_coupling(1, 1, 0, net_slots, CouplingMethod::Control)
+                        .with_coupling(2, 2, 0, net_slots, CouplingMethod::Control)
+                    ;
+
+                    params = couple_asymmetric_inverter(&params, 0 /* sender core */, s0_loops, 1 /* slot offset */, net_slots);
+                    params = couple_asymmetric_buffer(&params, 1 /* sender core */, s0_loops, 1 + slots_per_asym /* slot offset */, net_slots);
+                    let name = asymmetric_inverter_name(&params, "46", 2*s0_loops + 1, init_flt);
+                    run_sim(
+                        &name,
+                        drive_map_3stack_with_init_inv_then_buff(init_flt),
+                        params,
+                    );
+                }
+            }
+        }
+    }
 }
 
 
@@ -4859,6 +4973,8 @@ fn run_sim<const C: usize, const R: usize>(
     driver.add_csv_renderer(&*format!("{}meas.csv", prefix), 1600, None);
     driver.add_csv_renderer(&*format!("{}meas-sparse.csv", prefix), 12800, None);
 
+    info!("populating initial geometry");
+
     driver.add_classical_boundary(sim_padding);
 
     //////// create the wires and toroids
@@ -4906,6 +5022,8 @@ fn run_sim<const C: usize, const R: usize>(
         }
     }
 
+    info!("populating measurements and stimui");
+
     //////// monitor some measurements
     if params.hardcoded_control_and_sense {
         for core in 0..num_cores {
@@ -4990,6 +5108,7 @@ fn run_sim<const C: usize, const R: usize>(
         driver.add_stimulus(s);
     }
 
+    info!("launching sim");
     driver.step_until(duration_frames);
-    println!("sim complete");
+    info!("sim complete");
 }