Commit Graph

27 Commits

Author SHA1 Message Date
e6af37bef4 move crates/{post -> applications/stacked_cores}/scripts 2022-09-19 17:59:05 -07:00
bb737db3f7 plot some datapoints about the stacked_cores inverters 2022-09-19 17:58:26 -07:00
990e71b5c9 app: stacked_cores: more multi-core experiments 2022-09-19 16:02:28 -07:00
5641dc12f1 app: stacked_cores: more experiments around multi-core setups with bias 2022-09-18 17:39:47 -07:00
e8fc3c355f scripts: document the conditions which lead to "stable" logic levels 2022-09-18 17:28:32 -07:00
a6e5cb7583 app: stacked_cores: add some more simulations 2022-09-16 17:15:51 -07:00
8917c4a562 app: stacked_cores: define a bunch more sims, especially ones with asymmetric wrappings
this complicates the implementation quite a bit...
i imagine this whole file will be axed someday and treated as a
temporary prototype... we'll see :^)
2022-09-13 00:49:48 -07:00
3e78c1e407 app: stacked_cores: more sims where we use a different loop count to couple S0/S1/S2 2022-09-12 00:32:00 -07:00
265706371d app: stacked_cores: vary the drive strength in the stacked-outside-with-direct-output-locked setup 2022-09-09 15:38:16 -07:00
518ef7df6d app: stacked_cores: new experiment for coupling cores "outside"
that is, direct couple non-adjacent cores, by routing the wires
_outside_ the core stack
2022-09-08 03:21:40 -07:00
6b154367c9 app: stacked_cores: more experiments 2022-09-07 15:53:04 -07:00
5cdedfee41 app: stacked_cores: new experiment where we write S1 -> {S0,S2} and then write *back* to S1 from these 2022-09-04 01:27:54 -07:00
b8878bde1d split stacked_cores_8xx.py 2022-09-04 01:15:41 -07:00
e076480791 post: add script to extract info from the stacked_core 8xx experiments 2022-09-04 00:52:13 -07:00
2f91418095 post: add doc-comments for these tools 2022-08-10 14:28:20 -07:00
4fe8be8951 when writing Measurements to a CSV, format them in a machine-readable manner
i haven't tested the ones which contains commas -- hopefully the CSV
encoder deals with these :-)
2022-08-10 01:34:37 -07:00
542d700f69 meas: finish porting to a concrete type.
this will in future let me more easily test each individual measurement
type
2022-07-30 20:56:19 -07:00
f4ac5de099 viewer: add docs 2022-07-29 13:57:17 -07:00
604f368f0d SerializeRenderer: render to GenericSim, not StaticSim 2022-07-29 13:27:05 -07:00
4f2345f608 rename GenericSim -> AbstractSim 2022-07-28 23:41:42 -07:00
71ab89c4c9 de-virtualize GenericSim
this should let us fold the GenericSim and MaterialSim traits together.
2022-07-28 22:22:07 -07:00
5c4b8d86f2 measurements: store to disk *after* evaluating them
i'm hoping to simplify a lot of serialization code with this
2022-07-28 21:43:48 -07:00
6206569f4a Fold SampleableSim and MaterialSim into one 2022-07-28 16:41:32 -07:00
1dd6a068ba replace 'StaticSim' with the SpirvSim type, material being the Vacuum 2022-07-27 16:22:32 -07:00
dc38457a8b don't re-export StaticSim from sim/mod.rs
this way we can clearly spot the legacy users.
2022-07-27 15:42:18 -07:00
2f0e52a09b split SimState out of sim/mod.rs -> sim/legacy.rs 2022-07-24 18:19:26 -07:00
a2d35782a1 lift the post-processing tools (viewer, csv, decimate) into their own crate
- these tools shouldn't need access to coremem internals.
- lifting them out reduces some dependencies in coremem-the-library.
- separation allows faster iteration in the coremem library while
  temporarily breaking the post-processing tools (specifically,
  those tools could take deps on a specific coremem version and thereby
  we split the update process into two, smaller steps).
2022-07-17 15:47:39 -07:00