6b51fcea02
spirv: cpu: inline most of this step logic
2022-07-27 12:42:44 -07:00
d0afca7e3f
spirv: gpu: simplify some of this entry_point passing
2022-07-27 12:39:15 -07:00
b134fd2373
types: Optional: remove the Into/From<Option> impls
...
they're no longer used
2022-07-27 12:34:32 -07:00
568d61c598
spirv: remove the Optionality around entry points: compute them statically with traits
2022-07-27 12:32:43 -07:00
baaeeb9463
spirv_backend: no need to re-export glam
2022-07-27 12:13:01 -07:00
4bb0bc09ad
spirv/cpu.rs: remove unused import
2022-07-27 12:08:31 -07:00
c85bee20f5
replace some assert's with debug_assert's; slightly more optimal Optional impls
2022-07-27 12:07:30 -07:00
f6a585852e
move the dimensioned operations out of the sim adapters and into step.rs
2022-07-26 18:43:41 -07:00
7d16e87b6e
spirv: port all backends to use R for the stimulus
...
particularly, this patches over a difference where the gpu backend
expected the stimulus to be R, while the CPU thought it should be f32.
that would likely have revealed a crash if we had tested it with f64
(TODO).
2022-07-26 18:16:10 -07:00
00dcfb170a
spirv_backend/support.rs: remove the re-export of DimensionedSlice
...
also add some docs
2022-07-26 18:08:03 -07:00
dbd666d272
move the dimensioned indexing out of spirv_backend and into coremem_types
...
this allows us to use it from the CPU implementation.
2022-07-26 18:03:21 -07:00
d93d14d260
spirv_backend: use RuntimeArray to remove all this UnsizedArray stuff
2022-07-26 15:58:23 -07:00
09f7c8acb9
spirv_backend: support: remove unused helpers
2022-07-26 13:36:42 -07:00
6e4133db4d
spirv backend: simplify the adapt.rs indexing by using the constructors previously created
2022-07-26 13:29:39 -07:00
68d8cdde42
move some of the VolumeSample instantiation into step.rs, out of cpu.rs
...
we can go further: the IndexDim type itself can be moved into step.rs -- maybe?
if it were to wrap a generic flat-indexable thing -- either a slice, or
an array ref.
2022-07-26 01:15:53 -07:00
92ab220110
spirv: test: remove legacy cpu-only tests
...
these tests are all covered by the backend-agnostic tests
2022-07-26 00:54:33 -07:00
972e0ba4fb
spirv: test: add TODO for moving the cpu tests to be backend-agnostic
2022-07-25 22:38:10 -07:00
d68c1b20be
spirv: test: port the last rgpu test to be backend-agnostic
2022-07-25 22:37:05 -07:00
a969969449
spirv: test: port mh_ferromagnet tests to backend-agnostic
2022-07-25 22:36:46 -07:00
04c6d05ab0
spirv: test: port mb_ferromagnet tests to be backend-agnostic
2022-07-25 22:28:43 -07:00
dc49cddc97
spirv: test: port conductor tests to backend_agnostic
2022-07-25 22:23:56 -07:00
3fa2c22438
spirv: test: port RngStimulus tests to both backends
2022-07-25 22:19:44 -07:00
a8be7279b3
spirv sim: port rgpu smoke tests to test both Gpu and Cpu backend generically
2022-07-25 21:52:08 -07:00
fee9a1c216
implement a CpuBackend for running the "spirv" simulations
...
UNTESTED
2022-07-25 17:58:22 -07:00
47e11474d2
parameterize SpirvSim over R: Real
2022-07-25 14:49:32 -07:00
a1784da1cf
spirv: parameterize over the SimBackend
2022-07-25 14:27:09 -07:00
b4ee42cfdf
spirv: rename WgpuData -> WgpuBackend
2022-07-25 14:11:58 -07:00
cf42ec2dd1
spirv: SimBackend: remove the Array3 use
2022-07-25 14:11:01 -07:00
567f088f98
spirv: hide the gpu ops behind a SimBackend trait
2022-07-25 13:59:28 -07:00
ff1d9867ab
parameterize WgpuData over the M type
2022-07-25 13:15:41 -07:00
0801a0dca3
spirv: remove bindings.rs
...
the one function which was in here previously is just inlined into
gpu.rs
2022-07-25 13:07:35 -07:00
7cf8ed9a7b
spirv: gpu.rs no longer references the super SpirvSim type
2022-07-25 13:06:00 -07:00
8c8e707407
spirv: move the stimulus application out of gpu.rs
2022-07-25 12:52:35 -07:00
5b8978f0ec
spirv: instantiate the backend in mod.rs, not gpu.rs
2022-07-25 12:47:39 -07:00
bd066331de
spirv: fix indendation
2022-07-25 12:45:07 -07:00
cfbd5547cb
spirv: move indexable check into the gpu.rs backend
2022-07-25 12:44:02 -07:00
d1765554fc
spirv/gpu.rs: don't hard-code Vec3<f32> size
...
in the future this may become parameterized
2022-07-25 12:36:50 -07:00
38a47a0054
split most of the GPU spirv sim stuff into its own file
2022-07-25 12:29:45 -07:00
2032e90688
spirv_bindings: remove the IntoFfi/FromFfi stuff
2022-07-25 00:55:43 -07:00
8a16a5ce30
lift SimMeta from spirv_backend -> coremem_types
2022-07-25 00:52:11 -07:00
15aaa3e893
move spirv_backend/sim.rs -> coremem_types/step.rs
2022-07-25 00:40:27 -07:00
5fec965549
Optional: derive fmt and serde traits based on feature flag
2022-07-25 00:35:57 -07:00
5490634fe7
move Optional out of spirv_backend and into coremem_types
2022-07-25 00:35:04 -07:00
9c7ef7ec88
spirv_backend: split the array operations out of sim.rs -> adapt.rs
2022-07-25 00:28:03 -07:00
8ab89640f2
spirv_backend: split out some of the spirv entry point adapters into adapt.rs
2022-07-25 00:21:20 -07:00
ebd2762d7a
spirv: sim: adjust so Step{E,H}Context does not use ArrayHandle
...
the specific way to accomplish this is touchy.
see <https://github.com/EmbarkStudios/rust-gpu/issues/312#issuecomment-738824131 >:
> So I'd say placing any of the spirv_std::storage_class types into an aggregate (including capturing it in a closure) is unsupported for now
in our specific case, we can't return a tuple where one element is a `&`
to a spirv Input, and another element is a `&mut` to a spirv Output.
when we have a struct, it can enclose either ONLY inputs,
or ONLY outputs -- not a mix.
i'm not 100% on how the Serialized stuff works, since it appears to
violate that. i guess that's exactly what this ArrayHandle stuff
achieves though.
2022-07-24 22:57:41 -07:00
05f5f75dd3
spirv: remove the ArrayHandleMut artifacts in Step{H,E}Context
...
this will make it easier to reuse these blocks on the CPU side.
2022-07-24 22:17:44 -07:00
b70cafa205
spirv support: fix an overly-constrained lifetime parameter in the array index fn
2022-07-24 21:51:20 -07:00
7286d272b9
move coremem/mat -> coremem/sim/legacy/mat
2022-07-24 18:31:11 -07:00
d0fcd9b657
hide legacy.rs behind a legacy/ dir
2022-07-24 18:20:58 -07:00
