colin 3f54b25cf1 app: stacked_cores: define 49-xx: a *typo'd* multi-stage inverter with parameterized conductivities ...

in fact, M2 is initialized improperly: this actually acts as an
(overpowered) single-clock-cycle inverter.

2022-10-24 21:49:10 -07:00

..

scripts

app: stacked_cores: define 49-xx: a *typo'd* multi-stage inverter with parameterized conductivities

2022-10-24 21:49:10 -07:00

src

app: stacked_cores: define 49-xx: a *typo'd* multi-stage inverter with parameterized conductivities

2022-10-24 21:49:10 -07:00

Cargo.toml

app: stacked_cores: 46-xx: complete some runs of an inverter cascaded into a buffer

2022-10-16 02:00:55 -07:00