colin 3f54b25cf1 app: stacked_cores: define 49-xx: a *typo'd* multi-stage inverter with parameterized conductivities ...

in fact, M2 is initialized improperly: this actually acts as an
(overpowered) single-clock-cycle inverter.

2022-10-24 21:49:10 -07:00

..

analyze_inverters.py

app: stacked_cores: 41-xx: complete start of 800um 16x 5:1 5e9 I sim, and remove it

2022-10-04 15:52:13 -07:00

fake_cores_db.py

app: stacked_cores: split the inverter plotting into submodules

2022-09-27 15:59:58 -07:00

inverter_characteristics.py

app: stacked_cores: fix flipped 41-xx measurements

2022-10-16 06:02:13 -07:00

levels_proto.py

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plot_inverters.py

app: stacked_cores: define 49-xx: a *typo'd* multi-stage inverter with parameterized conductivities

2022-10-24 21:49:10 -07:00

stacked_cores_8xx.py

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stacked_cores_9xx.py

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stacked_cores_12xx.py

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stacked_cores_17xx.py

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stacked_cores_18xx.py

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stacked_cores_24xx.py

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stacked_cores_28xx.py

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stacked_cores_29xx.py

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stacked_cores_33xx.py

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stacked_cores_34xx.py

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stacked_cores_36xx.py

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stacked_cores_37xx.py

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stacked_cores_38xx.py

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stacked_cores_39xx_and_earlier_db.py

app: stacked_cores: split the inverter plotting into submodules

2022-09-27 15:59:58 -07:00

stacked_cores_39xx.py

app: stacked_cores: enable 0.001-level precision for current setting

2022-10-24 02:40:58 -07:00

stacked_cores_40xx_db.py

app: stacked_cores: define 49-xx: a *typo'd* multi-stage inverter with parameterized conductivities

2022-10-24 21:49:10 -07:00

stacked_cores.py

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