31fd83eb34
apps: multi_core_inverter: setup for 4ns clock phases
...
double what they were before. gives more time for things to settle.
2022-08-12 14:42:17 -07:00
d379a7b0ee
app: multi_core_inverter: try a related experiment where S0 is initialized to logic low
2022-08-11 22:24:19 -07:00
831cbfa76c
app: multi_core_inverter: tune the state serializations
...
less frequent (for less disk space), and also save state
in a recoverable manner
2022-08-11 18:22:55 -07:00
c83a44299f
app: multi-core-inverter: fix S4 drive signal specification
...
there was a spuriuous high -> low transition
2022-08-11 15:24:26 -07:00
e23ab9efd7
app: multi_core_inverter: try a 5-stage inverter (each stage inverts)
...
we're diverging from the blog pretty far now.
but it turns out that, because of the inversion in Maxwell's
$\nabla x E = -dB/dT$ equation, the trivial wiring actually leads to
natural inverters.
2022-08-11 03:01:08 -07:00
652621e47a
app: multi_core_inverter: more precise clock management
...
try to control the edges when the clock is release to prevent ringing.
2022-08-10 16:39:56 -07:00
59a4419130
app: multi_core_inverter: more detailed drive cycle
2022-08-10 15:47:28 -07:00
46a53a4dde
app: multi_core_inverter: fix up the drive sequence
...
see the code comment for explanation.
2022-08-10 01:43:36 -07:00
3998d72d02
app: multi_core_inverter: drive all four cores for four clock cycles
2022-08-10 01:35:42 -07:00
1771973c6d
CurlStimulus: take axis
and center
directly from the Region
...
by taking more from the region, we'll be able to reuse common code
and also make this more testable
2022-08-09 22:10:16 -07:00
6f0e35ea35
multi_core_inverter: add some stimuli and measurements
2022-07-29 23:53:44 -07:00
26efc12c21
multi_core_inverter: abstractions to allow swapping out float impl and backend
2022-07-28 13:20:26 -07:00
fe47eb09f8
driver: rename new_with_state
-> new
2022-07-28 01:59:11 -07:00
7a6bbf06a5
driver: remove new_spirv
method
2022-07-28 01:52:09 -07:00
47e11474d2
parameterize SpirvSim over R: Real
2022-07-25 14:49:32 -07:00
67872de16f
clean up some unused code/imports
2022-07-23 16:27:43 -07:00
f8fccd957a
coremem_types: IsomorphicConductor, AnisomorphicConductor are now used by both spirv and cpu impls
2022-07-19 02:08:22 -07:00
89be8bf8dd
multi_core_inverter: add documentation for running/viewing results
2022-07-17 14:58:42 -07:00
87ff2f2329
multi_core_inverter: add the last core(s) and the sense wire
2022-07-15 22:15:47 -07:00
559cec3894
multi_core_inverter: add coupling wires
2022-07-15 22:12:40 -07:00
6a316a2f6f
multi_core_inverter: add the second core
2022-07-15 22:03:19 -07:00
7f3893c0db
multi_core_inverter: add the drive input
2022-07-15 21:56:12 -07:00
6c63c7dc7d
multi_core_inverter: add the ctl wire loop
2022-07-15 21:53:34 -07:00
0d199445f1
multi_core_inverter: populate with a single core, no wires
...
i'll add the rest later. i can't see this on the viewer, but maybe the
viewer just doesn't differentiate vacuum from non-vacuum when the fields
are identical?
2022-07-15 20:16:57 -07:00
b778acfd28
add a new crate where i'll explicitly simulate the inverter i hypothesize in an upcoming blog about this project
2022-07-15 17:13:41 -07:00