9d2fbf8b07
app: stacked_cores: expand the 48-xx run set
2022-10-31 20:49:11 -07:00
267a204e7e
app: stacked_cores: complete some more 51-xx runs with variable winding ratios
2022-10-29 01:05:51 -07:00
fc0ce9f083
app: stacked_cores: 51-xx: try some higher-current variants; schedule some 5:1 and 7:1 inverter runs
2022-10-28 05:18:18 -07:00
0c7df48234
app: stacked_cores: 51-xx: complete some experiments using single-clock cascaded cores
...
i'm able to get 0.8x amplification between the first and the third core.
this is *less* than the amplification i got when cascading only one core
of the first, so not likely a good direction to pursue, though i haven't
yet explored that much of the parameter space.
2022-10-28 02:43:12 -07:00
12f286c3c7
app: stacked_cores: prototype a 3-core/1-cycle inverter (51-xx)
...
we vary the conductivities, as with 50-xx. the hope is that with a
multi-core approach like this we might get >> 1.0x amplification in the
unloaded setup, which we can place into a loaded circuit and deal with
the ~70% loading penalty.
2022-10-27 18:31:39 -07:00
9c17d3b45d
app: stacked_cores: conclude 50-xx runs
2022-10-27 18:17:11 -07:00
57e12cbe32
app: stacked_cores: 50-xx: explore some more runs
...
got the amplification up to a bit over 0.3...
2022-10-26 08:08:15 -07:00
6af2d1d9e3
app: stacked_cores: complete some more 50-xx runs
2022-10-25 15:29:33 -07:00
cba2db6b10
app: stacked_cores: 50-xx: complete a run with high *control* conductivity, and schedule a few more
2022-10-25 05:37:54 -07:00
f4f672aab6
app: stacked_cores: fix 49-xx (now 50-xx) and run a few paramaterizations
2022-10-25 03:58:19 -07:00
3f54b25cf1
app: stacked_cores: define 49-xx: a *typo'd* multi-stage inverter with parameterized conductivities
...
in fact, M2 is initialized improperly: this actually acts as an
(overpowered) single-clock-cycle inverter.
2022-10-24 21:49:10 -07:00
3e331db374
app: stacked_cores: 48-xx: grab more detailed measurements for recent inverters
2022-10-24 06:53:03 -07:00
87e94d2182
app: stacked_cores: enable 0.001-level precision for current setting
2022-10-24 02:40:58 -07:00
21d41ff3d5
app: stacked_cores: 48-xx: run another 2e10 I parameterization
2022-10-24 02:37:05 -07:00
e526289fe9
app: stacked_cores: 48-xx: test the high-side of current for an already successful run
2022-10-24 00:26:37 -07:00
0e3212e624
app: stacked_cores: 48-xx: try a few more 10ns, 5e4 coupling cond runs
2022-10-23 21:04:43 -07:00
2b8c5d45c2
app: stacked_cores: finish a lower-current variant of the 48-xx 5e2/4e4 conductivity run
2022-10-22 08:05:13 -07:00
e1867ee541
app: stacked_cores: 48-xx: complete a very low control-conductivity run (2e2)
2022-10-22 05:37:34 -07:00
816d7edc38
app: stacked_cores: 48-xx: complete a few more runs with varied conductivity ratios
2022-10-22 01:24:18 -07:00
32c643ef13
app: stacked_cores: 48-xx: complete runs for 5e2/4e4 ctrl/coupling run
...
high slope (1.70) over a narrow domain
2022-10-21 20:33:51 -07:00
8a8823ffd8
app: stacked_cores: more 48-xx runs where we vary the coupling conductivity separate from the control conductivity
2022-10-21 19:19:55 -07:00
75a88887f0
app: stacked_cores: 48-xx: simulate a few more variants
...
got one with a 1.4x slope at the start.
that's novel across all inverters i've simulated to-date.
2022-10-21 09:54:20 -07:00
3dbdead1cb
app: stacked_cores: 48-xx: complete a few more runs
2022-10-21 05:13:28 -07:00
daf50324d7
app: stacked_cores: complete more 48-xx runs
2022-10-21 01:00:46 -07:00
6f57e17bef
app: stacked_cores: 48-xx: add some runs
2022-10-17 06:51:48 -07:00
7c0151220c
app: stacked_cores: new 48-xx sim which varies conductivities on a 2-core buffer
2022-10-17 04:32:30 -07:00
ee74163131
app: stacked_cores: complete a few runs of 46-xx where the output is floating
...
this sohws us that most of the load preventing M1 from switching is due
to us holding its *downstream* core steady.
if we could somehow make it so that the downstream core presented a
lower load to M1, then we could hold it steady while writing M0 -> M1.
this is similar to saying "make M0 -> M1 a circuit that amplifies A >> 1
and make M1 -> M2 a 1:1 circuit". then we can hold M2 low and still get
amplification A - 1.
then the question is how do we get A >> 1?
2022-10-17 03:40:03 -07:00
760dd0070f
app: stacked_cores: complete a few more 46-xx runs
2022-10-16 23:18:33 -07:00
ff2c79162c
app: stacked_cores: 47-xx: cascade two buffers and vary their parameterization
2022-10-16 17:21:10 -07:00
c458b3135b
app: stacked_cores: fix flipped 41-xx measurements
2022-10-16 06:02:13 -07:00
e8adf6eaa7
app: stacked_cores: include intermediate core values in the db for multi-core inverters
2022-10-16 05:20:55 -07:00
3498649312
42-xx: try some > 400um inverters
2022-10-16 04:58:00 -07:00
7ecd8fa881
app: stacked_cores: backfill some 40-xx parameterizations
2022-10-16 04:30:49 -07:00
226e4949d0
app: stacked_cores: minimize what we extrapolate from beyond the measured transfer domain
2022-10-16 04:28:44 -07:00
74858ee247
app: stacked_cores: add aliases for poorly formatted f32 strings
2022-10-16 02:29:31 -07:00
3614d00871
app: stacked_cores: sort all the inverters in the db
2022-10-16 02:12:47 -07:00
bc61fd0d0a
app: stacked_cores: 46-xx: complete some runs of an inverter cascaded into a buffer
...
the results aren't great :'(
2022-10-16 02:00:55 -07:00
33b0b76278
app: stacked_cores: plot what happens when one cascades an inverter into a buffer
2022-10-15 23:26:10 -07:00
d03818b58e
app: stacked_cores: try varying the number of control loops separately from the coupling loops
...
doesn't make a huge difference, apparently.
2022-10-15 21:45:37 -07:00
3a21cf7655
app: stacked_cores: try a 3-core inverter where the 3rd core is initialized LOW
...
theory being that this would placeless load on the intermediary core,
allowing it to transition more. but that wasn't actually the case.
2022-10-15 07:45:14 -07:00
8a3914d56d
app: stacked_cores: factor out the inverter wiring setup
2022-10-14 20:11:58 -07:00
5a61613381
app: stacked_cores: 43-xx: complete more current variations
2022-10-14 19:25:05 -07:00
997ac5f299
app: stacked_cores: 43-xx: complete some 600um runs
2022-10-14 08:18:38 -07:00
8407c2c8e8
app: stacked_cores: 43-xx: run more current variations
2022-10-13 21:53:30 -07:00
196e6c8790
app: stacked_cores: 43-xx: run a few 5x 3:1 current variations
2022-10-13 19:22:58 -07:00
b07da366f1
app: stacked_cores: 43-xx: ingest results
2022-10-13 17:27:16 -07:00
f4d637fc98
app: stacked_cores: new 43-xx experiment where we cascade two asymmetrically-wound inverters
2022-10-12 07:39:02 -07:00
1cfebb73e0
app: stacked_cores: complete a few more 42-xx runs
2022-10-12 03:42:25 -07:00
0bf7b379d6
app: stacked_cores: explore more 4x 7:1 parameterizations
2022-10-11 23:27:40 -07:00
2f097ab1a8
app: stacked_cores: 42-xx: explore more 9x 3:1 parameterizations
2022-10-11 21:26:17 -07:00
