be172d4371
remove the 'license' section
...
no need to state my ideals so in-your-face here. better to just omit any talk
of licensing, if i truly believe it to be irrelevant.
2022-11-07 03:19:53 -08:00
4407a8d3f7
app: stacked_cores: 53-xx: complete some more runs, including one where inputs are uncoupled
2022-11-07 02:46:24 -08:00
16525127a1
app: stacked_cores: 53-xx: complete a run which uses pos-windings != neg-windings
2022-11-05 18:54:10 -07:00
af4b5ffa32
app: stacked_cores: 53-xx: complete a 1:1 coupled buffer
...
slope is poor, hovering around a constant 0.75 transmission ratio.
2022-11-05 02:59:10 -07:00
1742172e6c
app: stacked_cores: 53-xx: add a 5:1 buffer
...
it seems to under-transfer compared to the 3:1 buffers.
this *might* be an issue of drive current -- unclear.
2022-11-04 06:11:08 -07:00
3ebcc550a0
app: stacked_cores: 53-xx: better constrain the interpolation, and plot slope
2022-11-04 06:10:04 -07:00
373c80793f
app: stacked_cores: improve the 52-xx plotting/interpolation
...
it's a little slow :-(
i'd guess the `score` function is the slowest part. can maybe get scipy
to do a dot-product for us?
2022-11-04 03:22:42 -07:00
df828b6299
app: stacked_cores: create a plot_53xx and refactor the surroundings
...
note that the interpolation is very BAD. i need to figure out better
sampling.
2022-11-03 21:21:07 -07:00
4023a67912
app: stacked_cores: ingest 53-xx buffer results
2022-11-03 20:26:17 -07:00
aee3796c29
app: stacked_cores: note about preservation
2022-11-03 05:46:58 -07:00
a45c0c4324
app: stacked_cores: new 53-xx run, where we buffer differential signals
2022-11-03 05:42:38 -07:00
47189dcc7e
app: stacked_cores: 52-xx: complete more or gate parameterizations
2022-11-03 04:39:06 -07:00
70e14b4578
app: stacked_cores: 52-xx: sort the runs naturally (natsort)
2022-11-03 01:09:12 -07:00
a754b6e01d
app: stacked_cores: 52-xx: capture more runs of existing or gates
2022-11-03 01:02:33 -07:00
286a267f75
app: stacked_cores: 52-xx: add some facilities for plotting 52-xx or gate runs
...
it's primitive; not the *best* results
2022-11-02 17:21:29 -07:00
ff68e57fa5
app: stacked_cores: 52-xx: collect the measurements into a db
2022-11-02 15:42:49 -07:00
87366cf473
app: stacked_cores: define an "or gate" sim + script for post-processing
...
extract transfer characteristics with e.g.
```
extract_meas.py ../../../out/applications/stacked_cores/52-or--0.0004rad-5000ctl_cond-20000coupling_cond-2000ps-100ps-3ctl-3coupling-3_1_winding-49999998976e0-drive- 2e-9 4e-9 8e-9
```
2022-11-01 00:11:50 -07:00
9d2fbf8b07
app: stacked_cores: expand the 48-xx run set
2022-10-31 20:49:11 -07:00
267a204e7e
app: stacked_cores: complete some more 51-xx runs with variable winding ratios
2022-10-29 01:05:51 -07:00
fc0ce9f083
app: stacked_cores: 51-xx: try some higher-current variants; schedule some 5:1 and 7:1 inverter runs
2022-10-28 05:18:18 -07:00
0c7df48234
app: stacked_cores: 51-xx: complete some experiments using single-clock cascaded cores
...
i'm able to get 0.8x amplification between the first and the third core.
this is *less* than the amplification i got when cascading only one core
of the first, so not likely a good direction to pursue, though i haven't
yet explored that much of the parameter space.
2022-10-28 02:43:12 -07:00
12f286c3c7
app: stacked_cores: prototype a 3-core/1-cycle inverter (51-xx)
...
we vary the conductivities, as with 50-xx. the hope is that with a
multi-core approach like this we might get >> 1.0x amplification in the
unloaded setup, which we can place into a loaded circuit and deal with
the ~70% loading penalty.
2022-10-27 18:31:39 -07:00
9c17d3b45d
app: stacked_cores: conclude 50-xx runs
2022-10-27 18:17:11 -07:00
57e12cbe32
app: stacked_cores: 50-xx: explore some more runs
...
got the amplification up to a bit over 0.3...
2022-10-26 08:08:15 -07:00
6af2d1d9e3
app: stacked_cores: complete some more 50-xx runs
2022-10-25 15:29:33 -07:00
cba2db6b10
app: stacked_cores: 50-xx: complete a run with high *control* conductivity, and schedule a few more
2022-10-25 05:37:54 -07:00
f4f672aab6
app: stacked_cores: fix 49-xx (now 50-xx) and run a few paramaterizations
2022-10-25 03:58:19 -07:00
3f54b25cf1
app: stacked_cores: define 49-xx: a *typo'd* multi-stage inverter with parameterized conductivities
...
in fact, M2 is initialized improperly: this actually acts as an
(overpowered) single-clock-cycle inverter.
2022-10-24 21:49:10 -07:00
3e331db374
app: stacked_cores: 48-xx: grab more detailed measurements for recent inverters
2022-10-24 06:53:03 -07:00
87e94d2182
app: stacked_cores: enable 0.001-level precision for current setting
2022-10-24 02:40:58 -07:00
21d41ff3d5
app: stacked_cores: 48-xx: run another 2e10 I parameterization
2022-10-24 02:37:05 -07:00
e526289fe9
app: stacked_cores: 48-xx: test the high-side of current for an already successful run
2022-10-24 00:26:37 -07:00
0e3212e624
app: stacked_cores: 48-xx: try a few more 10ns, 5e4 coupling cond runs
2022-10-23 21:04:43 -07:00
2b8c5d45c2
app: stacked_cores: finish a lower-current variant of the 48-xx 5e2/4e4 conductivity run
2022-10-22 08:05:13 -07:00
e1867ee541
app: stacked_cores: 48-xx: complete a very low control-conductivity run (2e2)
2022-10-22 05:37:34 -07:00
816d7edc38
app: stacked_cores: 48-xx: complete a few more runs with varied conductivity ratios
2022-10-22 01:24:18 -07:00
32c643ef13
app: stacked_cores: 48-xx: complete runs for 5e2/4e4 ctrl/coupling run
...
high slope (1.70) over a narrow domain
2022-10-21 20:33:51 -07:00
8a8823ffd8
app: stacked_cores: more 48-xx runs where we vary the coupling conductivity separate from the control conductivity
2022-10-21 19:19:55 -07:00
75a88887f0
app: stacked_cores: 48-xx: simulate a few more variants
...
got one with a 1.4x slope at the start.
that's novel across all inverters i've simulated to-date.
2022-10-21 09:54:20 -07:00
3dbdead1cb
app: stacked_cores: 48-xx: complete a few more runs
2022-10-21 05:13:28 -07:00
daf50324d7
app: stacked_cores: complete more 48-xx runs
2022-10-21 01:00:46 -07:00
6f57e17bef
app: stacked_cores: 48-xx: add some runs
2022-10-17 06:51:48 -07:00
7c0151220c
app: stacked_cores: new 48-xx sim which varies conductivities on a 2-core buffer
2022-10-17 04:32:30 -07:00
ee74163131
app: stacked_cores: complete a few runs of 46-xx where the output is floating
...
this sohws us that most of the load preventing M1 from switching is due
to us holding its *downstream* core steady.
if we could somehow make it so that the downstream core presented a
lower load to M1, then we could hold it steady while writing M0 -> M1.
this is similar to saying "make M0 -> M1 a circuit that amplifies A >> 1
and make M1 -> M2 a 1:1 circuit". then we can hold M2 low and still get
amplification A - 1.
then the question is how do we get A >> 1?
2022-10-17 03:40:03 -07:00
760dd0070f
app: stacked_cores: complete a few more 46-xx runs
2022-10-16 23:18:33 -07:00
ff2c79162c
app: stacked_cores: 47-xx: cascade two buffers and vary their parameterization
2022-10-16 17:21:10 -07:00
c458b3135b
app: stacked_cores: fix flipped 41-xx measurements
2022-10-16 06:02:13 -07:00
e8adf6eaa7
app: stacked_cores: include intermediate core values in the db for multi-core inverters
2022-10-16 05:20:55 -07:00
3498649312
42-xx: try some > 400um inverters
2022-10-16 04:58:00 -07:00
7ecd8fa881
app: stacked_cores: backfill some 40-xx parameterizations
2022-10-16 04:30:49 -07:00
